X5083_06 Datasheet, PDF (5/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

X5083
Principles of Operation
Power-on Reset
Application of power to the X5083 activates a power-on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. RESET
active also blocks communication to the device through the
SPI interface. When V_CC exceeds the device V_TRIP value for
200ms (nominal) the circuit releases RESET, allowing the
processor to begin executing code. While V_CC < V_TRIP
communications to the device are inhibited.
Low Voltage Monitoring
During operation, the X5083 monitors the V_CC level and
asserts RESET if supply voltage falls below a preset
minimum V_TRIP. The RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition and terminates any SPI communication in
progress. The RESET signal remains active until the voltage
drops below 1V. It also remains active until V_CC returns and
exceeds V_TRIP for 200ms.
When V_CC falls below V_TRIP, any communications in
progress are terminated and communications are inhibited
until V_CC exceeds V_TRIP for t_PURST.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle
the CS/WDI pin periodically to prevent a RESET signal. The
CS/WDI pin must be toggled from HIGH to LOW prior to the
expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits with no action taken by the microprocessor
these bits remain unchanged, even after total power failure.
V_CC Threshold Reset Procedure
The X5083 is shipped with a standard V_CC threshold (V_TRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V_TRIP is not exactly right, or if higher precision is
needed in the V_TRIP value, the X5083 threshold may be
adjusted. The procedure is described below, and uses the
application of a high voltage control signal.
Setting the V_TRIP Voltage
This procedure is used to set the V_TRIP to a higher voltage
value. For example, if the current V_TRIP is 4.4V and the new
V_TRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
To set the new V_TRIP voltage, apply the desired V_TRIP
threshold voltage to the V_CC pin and tie the WP pin to the
programming voltage V_P. Then send a WREN command,
followed by a write of Data 00h to address 01h. CS going
HIGH on the write operation initiates the V_TRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 01h.
Resetting the V_TRIP Voltage
This procedure is used to set the V_TRIP to a “native” voltage
level. For example, if the current V_TRIP is 4.4V and the new
V_TRIP must be 4.0V, then the V_TRIP must be reset. When
V_TRIP is reset, the new V_TRIP is something less than 1.7V.
This procedure must be used to set the voltage to a lower
value.
To reset the new V_TRIP voltage, apply the desired V_TRIP
threshold voltage to the Vcc pin and tie the WP pin to the
programming voltage V_P. Then send a WREN command,
followed by a write of data 00h to address 03h. CS going
HIGH on the write operation initiates the V_TRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 03h.
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FN8127.3
June 15, 2006