ISL6112 Datasheet, PDF (5/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

ISL6112
Pin Descriptions (Pin Numbers and Names are Related) (Continued)
PIN NUMBER
PIN NAME
PIN FUNCTION
1, 36
FAULTA, FAULTB
Fault Outputs: Open-drain, active-low. Asserted whenever the isolation protection trips due to a fault
condition (overcurrent, input undervoltage, over-temperature). Each pin requires an external pull-up
resistor to V_STBY. Bringing the slot’s ON pin low resets FAULT if FAULT was asserted in response to a
fault condition on one of the slot’s MAIN outputs (+12V or +3.3V). FAULT is reset by bringing the slot’s
AUXEN pin low if FAULT was asserted in response to a fault condition on the slot’s VAUX output. If a fault
condition occurred on both the MAIN and VAUX outputs of the same slot, then both ON and AUXEN must
be brought low to de-assert the FAULT output.
9, 28
FORCE_ONA
FORCE_ONB
Enable Inputs: Active-low, level-sensitive. Asserting a FORCE_ON input will turn on all three of the
respective slot’s outputs (+12V, +3.3V, and VAUX), while specifically defeating all protections on those
supplies. This explicitly includes all overcurrent and short circuit protections, and on-chip thermal
protection for the VAUX supplies. Additionally included are the UVLO protections for the +3.3V and
+12VMAIN supplies. The FORCE_ON pins do not disable UVLO protection for the VAUX supplies. These
input pins are intended for diagnostic purposes only. Asserting FORCE_ON will cause the respective slot’s
PWRGD and FAULT pins to enter their open-drain state. Note that the SMBus register set will continue to
reflect the actual state of each slot’s supplies. There is a pair of register bits, accessible via the SMBus,
which can be set to disable (unconditionally de-assert) either or both of the FORCE_ON pins -- See
CNTRL Register Bit D[2].
4, 38
GPI_A0, GPI_B0 General Purpose Inputs: The states of these two inputs are available by reading the Common Status
Register, Bits [4:5]. If not used, connect each pin to GND.
39, 40, 41
A2, A1, A0
SMBus Address Select Pins. Connect to ground or leave open in order to program device SMBus base
address. These inputs have internal pull-up resistors to VSTBY. Address programmed on rising VSTBY.
48
SDA
Bidirectional SMBus data line.
47
SCL
SMBus Clock Input.
37
INT
Interrupt Output. Open-drain, active-low. output. Asserted whenever a power fault is detected if the
INTMSK bit (CS Register Bit D[3]) is a logical “0”. This output is cleared by performing an “echo reset” to
the appropriate fault bit(s) in the STAT and/or CS registers. This pin requires an external pull-up resistor
to VSTBY.
17, 33, 46
GND
IC Reference pins. Connect together and tie directly to the system’s analog GND plane directly at the
device.
7, 18, 19, 20, 30
NC
Reserved: Make no external connections to these pins.
5
FN6456.0
September 28, 2007