ISL6112 Datasheet, PDF (16/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

Timing Diagrams
ISL6112
SCL
t₄
SDA
DATA IN
SDA
DATA OUT
t₂
t₅
t₃
FIGURE 15. SMBUS TIMING
VSTBY
+3.3V
UVLO
AUXEN
VIH
0
tPOR
VAUX_OUT
0
ILIM(AUX)
AUX_IOUT
ISTEADY-STATE
0
ON
0
12VOUT
0
3VOUT
0
PWRGD_
0
ILIM(3V)
I3VOUT
ISTEADY-STATE
0
VIL
VIH
tFLT
VIH
VIH
VIL
tFLT
FAULT_
0
INT*
0
*
*
* INT DE-ASSERTED BY SOFTWARE
FIGURE 16. HOT-PLUG INTERFACE OPERATION
ISL6112 DEVICE ADDRESS COMMAND BYTE TO ISL6112 DATA BYTE TO ISL6112
DATA S 1 0 0 0 A2 A1 A0 0 A 0 0 0 0 0 X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
START R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE
ACKNOWLEDGE
CLK
MASTER TO DEVICE TRANSFER,
i.e., DATA DRIVEN BY MASTER.
DEVICE TO MASTER TRANSFER,
i.e., DATA DRIVEN BY DEVICE.
FIGURE 17. WRITE_BYTE PROTOCOL
16
FN6456.0
September 28, 2007