ISL6112 Datasheet, PDF (22/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

ISL6112
Status Register Slot B (STATB)
8-Bits, Read-Only
TABLE 8. STATUS REGISTER, SLOT B (STATB)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
read-only
read-only
read-only
read/write
read-only
read/write
FAULTB
MAINB
VAUXB
VAUXBF
Reserved
12VBF
D[1]
read-only
Reserved
D[0]
read/write
3VBF
BIT(s)
FAULTB
FAULT Pin Status - Slot B
FUNCTION
MAINB
MAIN Enable Status - Slot B
VAUXB
VAUX Enable Status - Slot B
OPERATION
1 = Fault pin asserted (FAULTB pin is LOW) 0 = Fault pin
deasserted (FAULTB pin is HIGH) See Notes 13, 14,
and 15.
Represents the actual state (on/off) of the four Main
Power outputs for Slot B (+12V and +3.3V)
1 = MAIN Power ON
0 = MAIN Power OFF
Represents the actual state (on/off) of the Auxiliary
Power output for Slot B
1 = AUX Power ON
0 = AUX Power OFF
VAUXBF
Overcurrent Fault: VAUXB supply
D[3]
Reserved
12VBF
Over current Fault: +12V supply
D[1]
Reserved
3VBF
Over current Fault: 3.3V supply
Power-Up Default Value:
Command_Byte Value (R/W):
0000 0000_h = 00_h
0000 0101_b = 05_h
1 = Fault 0 = No fault
Always read as zero
1 = Fault 0 = No fault
Always read as zero
1 = Fault 0 = No fault
The power-up default value is 00_h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an overcurrent fault
condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert INT. The status of the FAULTB pin is not
affected by reading the Status Register or by clearing active status bits.
NOTES:
13. If FAULTB has been set by an overcurrent condition on one or more of the MAIN outputs, the ONB input must go LOW to reset FAULTB. If
FAULTB has been set by a VAUXB overcurrent event, the AUXENB input must go LOW to reset FAULTB. If an overcurrent has occurred on
both a MAIN output and the VAUX output of slot B, both ONB and AUXENB of the slot must go low to reset FAULTB.
14. Neither the FAULTB bits nor the FAULTB pins are active when the ISL6112 power paths are controlled by the System Management Interface.
When using SMI power path control, the AUXENB and ONB pins for that slot must be tied to GND.
15. If FORCE_ONB is asserted (low), the FAULTB pin will be unconditionally forced to its open-drain state. Note, though, that the value in the
FAULTB register bit is not affected by FORCE_ONB, but will instead continue to read as a high if no faults are present on Slot B, and as a low
if any fault conditions exist which would disable Slot B if FORCE_ONB was not asserted.
22
FN6456.0
September 28, 2007