ISL6112 Datasheet, PDF (18/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

ISL6112
For those SMI control applications where the FORCE_ON
inputs are needed for diagnostic purposes, the FORCE_ON
inputs must be enabled; that is, CNTRL Register Bit D[2]
should read Logical “0.” Once FORCE_ON inputs are
asserted, all output voltages are present with all circuit
protection features disabled, including over-temperature
protection on VAUX outputs. To inhibit FORCE_ON
operation, a Logical “1” shall be written to the CNTRL
Register Bit D[2] location(s)
HPI-ONLY CONTROL APPLICATIONS
In applications where the ISL6112 is controlled only by HPI,
SMBus signals SCL, SDA, and INT signals are connected to
VSTBY as shown in Figure 1. In this configuration, the
ISL6112’s FAULT outputs are activated after power-on-reset
and become asserted when:
Either or both external ON and AUXEN input signals are
asserted, AND
• 12VIN, 3VIN, or VSTBY input voltage is lower than its
respective ULVO threshold, OR
• The fast OC circuit isolation protection has tripped, OR
• The slow OC circuit isolation protection has tripped AND
its filter time-out has expired, OR
• The slow OC circuit isolation protection has tripped AND
Slot die temperature > +140°C, OR.
• The ISL6112’s global die temperature > +160°C
._{In order to clear FAULT outputs once asserted, either or both}
ON and AUXEN input signals must be deasserted. Please
see FAULT pin description for additional information. If the
FORCE_ON inputs are used for diagnostic purposes, both
FAULT and PWRGD outputs are deasserted once
FORCE_ON inputs are asserted.
Serial Port Operation
The ISL6112 uses standard SMBus Write_Byte and
Read_Byte operations for communication with its host. The
SMBus Write_Byte operation involves sending the devices
target address, with the R/W bit (LSB) set to the low (write)
state, followed by a command byte and a data byte. The
SMBus Read_Byte operation is similar, but is a composite
write and read operation: the host first sends the devices
target address followed by the command byte, as in a write
operation. A new “Start” bit must then be sent to the
ISL6112, followed by a repeat of the device address with the
R/W bit set to the high (read) state. The data to be read from
the part may then be clocked out. There is one exception to
this rule: If the location latched in the pointer register from
the last write operation is known to be correct (i.e., points to
the desired register within the ISL6112), then the
“Receive_Byte” procedure may be used. To perform a
Receive_Byte operation, the host sends an address byte to
select the target ISL6112, with the R/W bit set to the high
(read) state, and then retrieves the data byte. Figures 17, 18
and 19 show the formats for these data read and data write
procedures.
The Command Register is eight bits (one byte) wide. This
byte carries the address of the ISL6112’s register to be
operated upon. The command byte values corresponding to
the various ISL6112 register addresses are shown in Table 4.
Command byte values other than 0000 0XXX_b = 00_h – 07_h
are reserved and should not be used.
ISL6112 SMBus Address Configuration
The ISL6112 responds to its own unique SMBus address,
which is assigned using A2, A1, and A0. These represent
the 3 LSBs of its 7-bit address, as shown in Table 3. These
address bits are assigned only during power-up of the
VSTBY supply input. These address bits allow up to eight
ISL6112 devices in a single system. These pins are either
grounded or left unconnected to specify a logical 0 or logical
1, respectively. A pin designated as a logical 1 may also be
pulled up to VSTBY.
TABLE 3. ISL6112 SMBUS ADDRESSING
INPUTS
ISL6112 DEVICE ADDRESS
A2
A1
A0
BINARY
HEX
0
0
0
1000 000X*b
80h
0
0
1
1000 001Xb
82h
0
1
0
1000 010Xb
84h
0
1
1
1000 011Xb
86h
1
0
0
1000 100Xb
88h
1
0
1
1000 101Xb
8Ah
1
1
0
1000 110Xb
8Ch
1
1
1
1000 111Xb
8Eh
* Where X = “1” for READ and “0” for WRITE
18
FN6456.0
September 28, 2007