ISL6112 Datasheet, PDF (20/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

ISL6112
Status Register Slot A (STATUSA)
8-Bits, Read-Only
TABLE 6. STATUS REGISTER, SLOT A (STATA)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
read-only
read-only
read-only
read/write
read-only
read/write
FAULTA
MAINA
VAUXA
VAUXAF
Reserved
12VAF
D[1]
read-only
Reserved
D[0]
read/write
3VAF
BIT(s)
FAULTA
FAULT Status - Slot A
FUNCTION
OPERATION
1 = Fault pin asserted (FAULTA pin is LOW) 0 = Fault pin
deasserted (FAULTA pin is HIGH) See Notes 8, 9, and 10.
MAINA
MAIN Enable Status - Slot A
Represents the actual state (on/off) of the two Main Power
outputs for Slot A (+12V and +3.3V) 1 = Main Power ON 0 =
Main Power OFF
VAUXA
VAUX Enable Status - Slot A
Represents the actual state (on/off) of the Auxiliary Power
output for Slot A 1 = AUX Power ON 0 = AUX Power OFF
VAUXAF
D[3]
Overcurrent Fault: VAUXA supply
Reserved
1 = Fault 0 = No fault
Always read as zero
12VAF
Overcurrent Fault: +12V supply
D[1]
Reserved
3VAF
Overcurrent Fault: 3.3V supply
Power-Up Default Value:
Command_Byte Value (R/W):
0000 0000_b = 00_h
0000 0100_b = 04_h
1 = Fault 0 = No fault
Always read as zero
1 = Fault 0 = No fault
The power-up default value is 00_h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an overcurrent fault
condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert INT. The status of the FAULTA pin is not affected
by reading the Status Register or by clearing active status bits.
NOTES:
8. If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA. If
FAULTA has been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA. If an overcurrent has occurred on
both a MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset FAULTA.
9. Neither the FAULTA bits nor the FAULTA pins are active when the ISL6112 power paths are controlled by the System Management Interface.
When using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND.
10. If FORCE_ONA is asserted (low), the FAULTA pin will be unconditionally forced to its open-drain state. Note, though, that the value in the
FAULTA register bit is not affected by FORCE_ONA, but will instead continue to read as a high if no faults are present on Slot A, and as a low
if any fault conditions exist, which would disable Slot A if FORCE_ONA was not asserted.
20
FN6456.0
September 28, 2007