ISL6112 Datasheet, PDF (12/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

ISL6112
where I_LIM = 50mV/R_SENSE and C_LOAD is the load
capacitance. As a consequence, the CR duration, t_FILTER,
must be programmed to exceed the time it will take to fully
charge the output load to the input rail voltage level.
MAIN Outputs (Start-up Delay and Slew-Rate
Control)
The 3.3V outputs act as source followers. In this mode of
operation, V_SOURCE = [V_GATE – V_TH(ON)] until the
associated output reaches 3.3V. The voltage on the gate of
the MOSFET will then continue to rise until it reaches 12V,
which ensures minimum r_DS(ON). For the 12V outputs, when
the MOSFET is optionally configured as a Miller integrator to
adjust the V_OUT ramp time by having a C_GD capacitor,
which is connected between the MOSFET’s gate and drain.
In this configuration, the feedback action from drain to gate
of the MOSFET causes the voltage at the drain of the
MOSFET to slew in a linear fashion at a rate estimated by
Equation 3:
dv/dt VOUT
NOMINALLY
=
2_----5_----μ_----A_--
C_GD
(EQ. 3)
Table 1 approximates the output slew-rate for various values
of C_GATE when start-up is dominated by GATE capacitance
(external C_GATE from GATE pin to ground plus C_GS of the
external MOSFET for the 3.3V rail; C_GD for the 12V rail).
TABLE 1. 3.3V AND 12V OUTPUT SLEW-RATE SELECTION
FOR GATE CAPACITANCE DOMINATED START-UP
| IGATE | = 25µA
CGATE or C_GD
0.01µF*
dv/dt (load)
2.5V/ms
0.022µF*
1.136V/ms
0.047µF
0.532 V/ms
0.1µF
0.250V/ms
*Values in this range will be affected by the internal parasitic
capacitances of the MOSFETs used, and should be verified
experimentally.
Note that all of these performance estimates are useful only for
first order time and loading expectations as they do not look at
other significant loading factors. Figures 3, 4, 5, 6 and 7
illustrate empirically the discussed turn-on performance with the
noted loading and compensation conditions.
Notice the degree of control over the in-rush current and the
GATE ramp rate as the and values are changed thus providing
for highly customizable turn-on characteristics.
In some scope shots although the C_FILTER shows a ramping
in the absence of excessive displayed loading current the
C_FILTER is responding to the other MAIN supply current that
is not displayed.
All scope shots were taken from the ISL6112EVAL1Z with
any component changes noted.
12V_OUT
12V_GATE
12I_OUT
C_FILTER
C_GD = 6800pF
C_GS = 22nF
FIGURE 3. 12VMAIN START-UP R_LOAD = 10Ω,
C_LOAD = 470µF
3V_OUT
3V_GATE
3I_OUT
C_FILTER
C_FILTER RESPONDING TO UNSHOWN MAIN SUPPLY
C_GATE = 22nF
FIGURE 4. 3VMAIN START-UP R_LOAD = 2Ω, C_LOAD = 470µF
12V_OUT
12V_GATE
12I_OUT
C_FILTER
C_GD = 6800pF
C_GS = 2200pF
FIGURE 5. 12VMAIN START-UP RLOAD = 10Ω,
C_LOAD = 470µF
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FN6456.0
September 28, 2007