ISL6112 Datasheet, PDF (15/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

ISL6112
For the ISL6112, there is a minimum t_FILTER consideration
since the ISL6112 has its CR feature invoked as it turns-on the
FETs into the load. There is a maximum bulk capacitance
specified for each power level supported that needs to be
charged at the CR limit. This in-rush current time must be
considered when determining the t_FILTER duration.
TABLE 2.
NOMINAL t_FILTER DURATION
C_FILTER CAPACITANCE (µF)
TIME (ms)
Open
0.01
0.01
5
0.022
11
0.047
24
0.1
50
NOTE: Nominal CR_DUR = C_FILTER cap (μF) * 500kΩ.
.
Power-Down Cycle
When a slot is turned off either under HPI or SMI control ,
internal discharge FETs are connected to the output load
providing a discharge path for load capacitance connected to
the part’s outputs ensuring that the outputs are pulled to
GND. This is a compliancy requirement if a replacement add
in card will be inserted into the slot.
Thermal Shutdown
The internal VAUX MOSFETs are protected against damage
not only by current limiting, but by a dual-mode
over-temperature protection scheme as well. Each slot
controller on the ISL6112 is thermally isolated from the other.
Should an overcurrent condition raise the junction
temperature of one slot’s controller and pass elements to
+140°C, all of the outputs for that slot (including VAUX) will
be shut off and the slots FAULT output will be asserted. The
other slots operating condition will remain unaffected.
However, should the ISL6112’s die temperature exceed
+160°C, both slots (all outputs, including VAUXA and
VAUXB) will be shut off, whether or not a current limit
(1)
AUXEN
(2)
VAUX
(3)
3VAUX_UV
(1)
ON
(4)
MAIN
(3)
12VOUT_UV
3VOUT_UV
(3)
(1)
FORCE_ON
(5)
FORCE_EN
condition exists. A +160°C over-temperature condition
additionally sets the over-temperature bit (OT_INT) in the
“Common Status Register (CS) 8-Bits, Read/Write” on
page 23.
PWRGD Outputs
The ISL6112 has two PWRGD outputs, one for each slot.
These are open-drain, active-low outputs that require an
external pull-up resistor to VSTBY. Each output is asserted
when a slot has been enabled and has successfully begun
delivering power to its respective +12V, +3.3V, and VAUX
outputs. An equivalent logic diagram for PWRGD is shown in
Figure 14.
FORCE_ON Inputs
These level-sensitive, active-low inputs are provided to facilitate
designing or debugging systems using the ISL6112. Asserting
FORCE_ON will turn on all three of the respective slot’s
outputs (12MAIN, 3MAIN, and VAUX), while specifically
defeating all overcurrent and short circuit protections, and on-
chip thermal protection for the VAUX supplies. Additionally,
asserting FORCE_ON will disable all of the input and output
UVLO protections, with the sole exception of the VSTBY input
UVLO.
Asserting FORCE_ON will cause the slot PWRGD and
FAULT outputs to enter their open-drain state. Additionally,
there are two SMBus accessible register bits (See Control
Register Bit D[2] in Tables 5 and 7), which can be set to
disable the corresponding slot’s FORCE_ON pins. This
allows system software to prevent these hardware
overrides from being inadvertently activated during normal
use. When not used, each FORCE_ON pin can be
connected to VSTBY using an external pull-up resistor or
simply shorted to VSTBY.
General Purpose Input (GPI) Pins
Two pins on the ISL6112 are available for use as GPI pins. The
logic state of each of these pins can be determined by polling
Bits [4:5] of Common Status Register. Both of these inputs are
compliant to 3.3V. If GPI is unused, connect each to GND.
VSTBY
PWRGD
(1) _{External pin}
(2) _{CNTRL Register Bit D[0]}
(3) _{Internal flag}
(4) _{CNTRL Register Bit D[1]}
(5) _{CNTRL Register Bit D[2]}
FIGURE 14. PWRGD LOGIC DIAGRAM
15
FN6456.0
September 28, 2007