ISL6112 Datasheet, PDF (17/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

ISL6112
Timing Diagrams (Continued)
ISL6112 DEVICE ADDRESS COMMAND BYTE TO ISL6112
ISL6112 DEVICE ADDRESS DATA READ FROM ISL6112
DATA S 1 0 0 0 A2 A1 A0 0 A 0 0 0 0 0 X X X A S 1 0 0 0 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 /A P
START
R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE START
R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE
CLK
MASTER TO DEVICE TRANSFER,
i.E., DATA DRIVEN BY MASTER.
DEVICE TO MASTER TRANSFER,
i.e., DATA DRIVEN BY DEVICE.
FIGURE 18. READ_BYTE PROTOCOL
ISL6112 DEVICE ADDRESS
BYTE READ FROM ISL6112
DATA S 1 0 0 0 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 /A P
START ^{R/W = READ}
ACKNOWLEDGE NOT ACKNOWLEDGE STOP
CLK
MASTER TO DEVICE TRANSFER,
i.e., DATA DRIVEN BY MASTER.
DEVICE TO MASTER TRANSFER,
i.e., DATA DRIVEN BY DEVICE.
FIGURE 19. RECEIVE_BYTE PROTOCOL
Hot-Plug Interface (HPI)
Once the input supplies are above their respective UVLO
thresholds, the Hot-Plug Interface can be utilized for power
control by enabling the control input pins (AUXEN and ON)
for each slot. In order for the ISL6112 to switch on the VAUX
supply for either slot, the AUXEN control must be enabled
after the power-on-reset delay, t_POR (typically, 250µs), has
elapsed.
System Management Interface (SMI)
The ISL6112’s System Management Interface uses the
Read_Byte and Write_Byte subset of the SMBus protocols
to communicate with its host via the System Management
Interface bus. The INT output signals the controlling
processor that one or more events need attention, if an
interrupt-driven architecture is used. Note that the ISL6112
does not participate in the SMBus Alert Response Address
(ARA) portion of the SMBus protocol.
Fault Reporting and Interrupt Generation
SMI ONLY CONTROL APPLICATIONS
In applications where the ISL6112 is controlled only by the
SMI, ON and AUXEN are connected to GND and the
FORCE_ON pins are connected to VSTBY either as shown
in Figure 1 or shorted. In these cases, the ISL6112’s FAULT
outputs and STATUS Register Bit D[7] (FAULT) are not
activated as fault status is determined by polling STATUS
Register Bits D[4], D[2], D[0] and CS (Common Status)
Register Bits D[2:1]. Individual fault bits in STAT and CS
registers are asserted after power-on-reset when:
• Either or both CNTRL Register Bits D[1:0] are asserted,
AND
• 12VIN, 3VIN, or VSTBY input voltage is lower than its
respective ULVO threshold, OR
• The fast OC circuit isolation protection has tripped, OR
• The slow OC circuit isolation protection has tripped AND
its filter time-out has expired, OR
• The slow OC circuit isolation protection has tripped AND
Slot die temperature > +140°C, OR
• The ISL6112’s global die temperature > +160°C
Once asserted, to clear any one or all STATUS Register Bits
D[4], D[2], D[0] and/or CS Register Bits D[2], D[1], a
software subroutine can perform an “echo reset” where a
Logical “1” is written back to those register bit locations that
have indicated a fault. This method of “echo reset” allows
data to be retained in the STATUS and/or CS registers until
such time as the system is prepared to operate on that data.
The ISL6112 can operate in interrupt mode or polled mode.
For interrupt-mode operation, the open-drain, active-LOW
INT output signal is activated after power-on-reset if the
INTMSK bit (CS Register Bit D[3]) has been reset to Logical
“0”. Once activated, the INT output is asserted by any one of
the fault conditions previously listed and deasserted when
one or all STAT Register Bits D[4], D[2], D[0] and/or CS
Register Bits D[2], D[1] are reset upon the execution of an
SMBus “echo reset” WRITE_BYTE cycle. For polled-mode
operation, the INTMSK bit should be set to Logical “1,”
thereby inhibiting INT output pin operation.
17
FN6456.0
September 28, 2007