ISL6112 Datasheet, PDF (23/31 Pages) Intersil Corporation – Dual Slot PCI-Express Power Controller

ISL6112
Common Status Register (CS)
8-Bits, Read/Write
TABLE 9. COMMON STATUS REGISTER (CS)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
read-write
read-write
read-only
read-only
read-write
read-write
Reserved
Reserved
GPI_B0
GPI_A0
INTMSK
UV_INT
D[1]
read-write
OT_INT
D[0]
read-only
Reserved
BIT(s)
D[7]
Reserved
FUNCTION
OPERATION
Always read as zero
D[6]
GPI_B0
GPI_A0
INTMSK
Reserved
General Purpose Input 0, Slot B
General Purpose Input 0, Slot A
Interrupt Mask
UV_INT undervoltage Interrupt
OT_INT over-temperature Interrupt
D[0]
Reserved
Power-Up Default Value: 00000000_b = 00_h
Command_Byte Value (R/W): 00000110_b = 06_h
Always read as zero
State of GPI_B0 pin
State of GPI_A0 pin
0 = INT generation is enabled
1 = INT generation is disabled.
The ISL6112 does not participate in the SMBus Alert
Response Address (ARA) protocol
0 = No UVLO fault
1 = UVLO fault
Set whenever a circuit isolation protection fault condition
occurs as a result of an undervoltage lockout condition on
one of the main supply inputs. This bit is only set if a UVLO
condition occurs while the ON pin is asserted or the MAIN
control bits are set
0 = Die Temp < +160°C.
1 = Fault: Die Temp > +160°C.
Set if a fault occurs as a result of the ISL6112’s die
temperature exceeding +160°C
Undefined
To reset the OT_INT and UV_INT fault bits, a logical 1 must be written back to these bits.
23
FN6456.0
September 28, 2007