ISL5216_07 Datasheet, PDF (43/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
P(31:0)
31:0
TABLE 34. FILTER COMPUTE ENGINE INSTRUCTION RAMS (IWA = *100h THRU *17Fh)
FUNCTION
These locations in RAM are used to store the Filter Compute Engine instruction words. There are 128 bits per instruction word with
each word consisting of condition code selects, FIR parameters and data routing controls. The filter compute engine is controlled by
a simple sequencer supporting up to 32 steps where each step is defined by a 128-bit instruction word. This instruction word is
assigned to RAM memory in four 32-bit data writes through the Microprocessor Interface starting with the low 32 bits. Hence, 128
32-bit memory locations are required per channel to support the 32 steps of the Filter Sequencer. See the Filter Compute Engine and
Filter Sequencer sections of the data sheet for more details.
P(15:0)
TABLE 35. FILTER COMPUTE ENGINE INSTRUCTION POINTER RAMS (IWA = *180h THRU *1FCh)
FUNCTION
(no programming required)
P(31:0)
31:8
TABLE 36. FILTER COMPUTE ENGINE COEFFICIENT RAM (IWA = *440h THRU *4FFh)
FUNCTION
These locations in RAM are used to store the 22-bit filter coefficients used by the Filter Compute Engine of each channel in
implementing a FIR filter. The 22-bit FIR filter coefficients are loaded in the upper 22 bits of each 32-bit RAM location. The two LSBs
of the second byte (bits 9:8 of the total 32 bits, 31:0) are the shift bits. These are set to zero if not used. The least significant byte
(bits 7:0 of the total 32 bits, 31:0) are ignored. The coefficient RAM address space allows for storage of 192 filter coefficients storage
locations. See the Filter Compute Engine and Filter Sequencer sections of the data sheet for more details.
Tables of Global Write Address (GWA) Registers
NOTE: These Global Write Addresses control global functions on the ISL5216, so they are not repeated for each channel. The top five address bits
select this set of registers (F8XXh).
TABLE 37. TEST CONTROL REGISTER (GWA = F800h)
P(31:0)
FUNCTION
31:21
These bits can be routed to the output pins by setting bit 16 below. The bit to pin mapping is:
31 = Intrpt
30 = SYNCO 29 = SERCLK (unless x1 CLK is selected)
28 = SYNCA 27 = SYNCB 26 = SYNCC 25 = SYNCD
24 = SD1A
23 = SD1B
22 = SD1C
21 = SD1D
This is provided for testing board level interconnects. To control the SERCLK output, a divided down clock must be selected in the
serial clock control register (GWA = F803h).
20:17 Unused - set to zero.
16
This bit, when high, routes bits 31:17 to the output pins in place of the normal outputs.
15
Data RAM test access enable: set to 1 to access data RAM for testing, set to 0 for normal operation
14:10 Unused - set to zero.
9
Set to 0.
8
Set to 0.
7:4
These bits, when set, route the MSB of the SIN output of the channel’s carrier NCO to the number two serial output pin in place of
the normal output. 7=CH0 6=CH1 5=CH2 4=CH3.
3
Offset I PN by XORing bit 10 of the PN generator with the output PN.
2
Enable (2²³ - 1) PN generator. The PN signal that can be added to the mixer output of each channel is produced from a (2²³ - 1)
sequence, a (2¹⁵ - 1) sequence or both. Two separate generators are provided. The outputs of both are XORed together to extend
the repeat period. Either or both generators can be disabled. The XORed output can further be XORed with a delayed version of the
(2²³ - 1) sequence on the I channel to decorrelate it from the Q channel. Otherwise, the same sequence will be used on both I and Q.
1
Enable (2¹⁵ - 1) PN generator.
0
Test mode. When asserted, this bit puts the chip into internal (self) test mode.
Set to 1 to enter a Self Test Mode.
43
FN6013.3
July 13, 2007