ISL5216_07 Datasheet, PDF (41/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
P(31:0)
31:24
23:16
15:8
7:0
TABLE 26. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA = *015h)
FUNCTION
Fourth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 31:24.
Third serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 23:16.
Second serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 15:8.
First serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D.
Bit
Function
7
Sync generated. When set, a sync pulse is generated with the data slot (Serial Data Output 1 only, i.e., the sync is only
associated with Output 1). Set to zero for Output 2, SD2x.
6:3
Word width/format. All fixed point data is twos complement. The data is rounded (asymmetrically, with saturation) to the
desired number of bits.
0000
0-bit, fixed point (actually 1-bit position is used).
0001
4-bit, fixed point.
0010
6-bit, fixed point.
0011
8-bit, fixed point.
0100
10-bit, fixed point.
0101
12-bit, fixed point.
0110
16-bit, fixed point.
0111
20-bit, fixed point.
1000
24-bit, fixed point .
1001
32-bit fixed (8 LSBs are zeroed).
1010
32-bit, floating point, IEEE format.
All other codes are invalid.
Note: Floating point format is only available on the Serial Data Output 1. Code 1010 is invalid on Serial Data Output 2.
2:0
Data type
000
Zeros
001
I1 (data routed from FIFO and AGC path).
010
Q1 (data routed from FIFO and AGC path).
011
Magnitude of I1/Q1.
100
Phase (or dφ/dt) of I1/Q1.
101
I2 (data routed directly from the filter processor).
110
Q2 (data routed directly from the filter processor).
111
AGC gain of I1/Q1 path.
The filter processor must be programmed appropriately to route the data to I1/Q1 or I2/Q2.
NOTE:
Disable a slot by setting the 8-bit word to 00h. When disabled, a slot still uses one clock period. If, for example, the slots are
programmed to 16-bit, disabled, 16-bit, there would a one clock idle period between the two 16-bit data words.
If a new data sample occurs before the current set of data has been output, the new data will preempt the output and the first slot of
the new data will begin immediately. If a late sync was programmed, it will not occur.
0 1 2 3 4 5 6 7 8 9 ABCDEF 0 1 2 3 4 5 6 7 8 9 ABCDEF
I, Q
012345678901234567890123ZZZZZZZZ
MAG
Z 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 Z Z Z Z Z Z Z Z (MSB zero unless shifted)
PH
012345678901234567ZZZZZZZZZZZZZZ
AGC
Z 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 Z Z Z Z Z Z Z Z Z Z Z Z Z Z (MSB zeroed)
P(31:0)
31:24
23:16
15:8
7:0
TABLE 27. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 2 (IWA = *016h)
FUNCTION
Set to zero.
Seventh serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 23:16.
Sixth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 15:8.
Fifth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 7:0.
41
FN6013.3
July 13, 2007