ISL5216_07 Datasheet, PDF (32/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
JTAG
JTAG: The IEEE1149.1 Joint Test Action Group boundary
scan standard operational codes shown in Table 3 below are
supported. A separate application note is available with
implementation details.
TABLE 3. JTAG OP CODES SUPPORTED
INSTRUCTION
OP CODE
EXTEST
0000
IDCODE
0001
SAMPLE/PRELOAD
0010
INTEST
0011
BYPASS
1111
Built in Self Test
Self-test is initiated by resetting the part and loading a given
configuration register set and filter coefficient set. The self-
test replaces the user programmed input with a PN
sequence and calculates a 16 bit signature from the output
data. This signature is compared to a user-provided
signature and the result is provided as a bit in the status
register. The BIST procedure is as follows:
1. Configure the part as described in “Recommended
ISL5216 configuration procedure following a hardware
reset” above.
2. (optional) Load the 16 bit comparison signature into GWA
F80BH bits 15:0. This value will be compared to the
device-calculated signature and reported in the status
register. The device-calculated signature may also be
read and the comparison performed in the user’s
microcontroller.
3. Write 00000000H to F019H to perform a software reset of
all channels.
4. Write 00000001H to GWA F800H to start the first phase
of the self test.
5. Wait until bit 0 of F800H is cleared indicating the first
phase of self test has completed.
6. Write 00000000H to F019H to reset all channels again.
7. Write 00000001H to GWA F800H to start the second
phase of the self test.
8. Wait until bit 0 of F800H is cleared indicating the second
phase of self test has completed.
9. If a comparison signature has been supplied (step 2), bit
12 of the status register (direct read address register 3) is
set to 1 if the signature matches the ISL5216-generated
signature.
10. The ISL5216-generated signature may be read from
GWA F80BH bits 31:16. The user-supplied signature
(step 2) may be also be read back from bits 15:0.
Filter Compute Engine Data RAM Test
The ISL5216 provides read/write access to the data RAM
used by a channel’s filter compute engine. To access the
data RAM for testing, set bit 15 of GWA F800H. Data must
be written to the RAM in Q/I pairs - 24 bit Q first, then 24 bit I.
Q and I samples are written to the RAM using the indirect
addresses shown in the table below (see To Write to the
Internal Registers above for the indirect write procedure).
Reading of the registers may occur in any order. The table
below provides the valid address range in data RAM test
mode. Note that addresses *000H - *6FFH are valid with the
exception of *300H - *3FFH. * = 0, 1, 2, or 3 for channels 0
through 3, respectively. F800H bit 15 must be cleared after
data RAM testing to return to normal operation.
DATA RAM ADDRESS MAP
INDIRECT ADDRESS (Note 18)
DATA
*000H
Q sample 0
*001H
I sample 0
*002H
Q sample 1
*003H
I sample 1
:
:
*2FEH
Q sample 767
*2FFH
I sample 767
*300H - *3FFH
unused
*400H
Q sample 768
*401H
I sample 768
*402H
Q sample 769
*403H
I sample 769
:
:
*6FEH
Q sample 1535
*6FFH
I sample 1535
*700H - *7FFH
unused
NOTE:
18. Denotes 0, 1, 2 or 3 for channels 0 - 3, respectively.
32
FN6013.3
July 13, 2007