ISL5216_07 Datasheet, PDF (38/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
P(31:0)
14
13:12
11:0
TABLE 15. FILTER COMPUTE ENGINE/RESAMPLER CONTROL REGISTER (IWA = *00Ah) (Continued)
FUNCTION
Enable RS freq offset. This bit, when set, enables the serially loaded resampler offset frequency word. When zero, the offset is
zeroed. To disable the shifting, see IWA register *000h.
Serial input word size. These bits select the number of bits in the resampler offset frequency word (loaded serially via
SOF/SOFSYNC).
00 8 bits
01 16 bits
10 24 bits
11 32 bits
FIFODelay. A FIFO is provided at the output of the filter compute engine to smooth the sample spacing when using the resampler or
interpolation FIRs. In these filters, the outputs can be produced in bursts or with gaps. The FIFO takes the samples in and outputs
them based on a counter timeout. If the FIFO is empty and the counter is at its terminal count (hold state), the data is passed through
and the counter is reloaded. If the counter is not at terminal count, the data is held in the FIFO until the counter times out. The FIFO
can hold up to 4 samples. The delay is programmed in clock periods. The value programmed is one less than the number of clocks
of delay. Set to 0 for a delay of one (fall through). The delay should be programmed to slightly less than the desired spacing to prevent
overflow.
P(15:0)
13:9
8:0
TABLE 16. FILTER START OFFSET REGISTER (IWA = *00Bh)
FUNCTION
RAM Instruction number to which the offset is applied. 0–31. Aliasing applies. Used for polyphase filters.
Amount of offset. Offsets the data RAM address for filter #n. This is used to offset the channels from each other when breaking the
processing up among multiple channels for polyphase filters. For example, four channels can receive the same data at 8MSPS, filter
and decimate by 8 to output at 1MHz. If the computations are offset by two samples each, then the outputs of the four channels can
be multiplexed together to get an output sample rate of 4MSPS. With a 64MSPS clock, the composite filter could have more than
100 taps where a single channel would only be capable of around 24 taps at a 4MHz output.
EXCEPT IN VERY RARE CIRCUMSTANCES, THIS VALUE SHOULD BE A NEGATIVE NUMBER.
P(31:0)
31
30
29:20
19:10
9:0
TABLE 17. WAIT THRESHOLD/DECREMENT VALUE REGISTER (IWA = *00Ch)
FUNCTION
μPTestBit. This bit is provided as a microprocessor controlled condition code for the filter compute engine for conditional execution
or synchronous startup. Active high.
Set to 0.
Decrement value 1. Positive number.
Decrement value 0. Positive number. Usually set equal to the Threshold (bits 9:0).
Threshold. Number of samples needed to run a filter set and produce an output.
P(15:0)
15:9
8:0
TABLE 18. RESET WRITE POINTER OFFSET REGISTER (IWA = *00Dh)
FUNCTION
Set to zero.
This parameter is the offset between filter compute engine read and write pointers on filter compute engine reset. On reset, the read
and write pointers for all the filters are loaded, the read pointer with zero and the write pointer with this value. Set to 0 for a single
filter and 2 for a multi-filter chain.
P(15:0)
15:0
TABLE 19. AGC GAIN LOAD REGISTER (IWA = *00Eh)
FUNCTION
This location loads the AGC accumulator. If the loop attack/decay gain is set to zero and this value is within the AGC gain limits, the
AGC will hold this value. If not, the AGC will be set to this gain (or to a limit) and then start to settle.
format is four exponent bits (15:12), and 12 mantissa bits, (11:0).
38
FN6013.3
July 13, 2007