ISL5216_07 Datasheet, PDF (17/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
65.536MHz/4 = 16.384MHz, where the factor of 4 is the CIC
decimation we have chosen.
Each channel computes the same sequence, offset by one
output sample from the previous sample (see IWA = *00Bh).
Each channel decimates down to 2.048M and then the
channels are multiplexed together in the output formatter to
get the desired 8.192MSPS. The input sample rate to the
final filter of each channel must meet Nyquist requirements
for the final output to assure that no information is lost due to
aliasing.
SAMPLE FILTER #4 PROGRAM
STEP
INSTRUCTION
0
Wait for enough input samples (8 in this case)
1
FIR
type = even symmetry
44 taps
decimate by 8
compute one output
memory block size 64
memory block start at 0
coefficient block start at 64
step size 1
output to AGC
offset memory read pointers by 0, -2, -4, -6
2
Jump, Unconditional, to 0
The number of FIR taps available for these requirements is
calculated as follows:
65536/2048 = 32 clocks
minus (8 writes + 1 wait + 1 jump = 10 clocks)
= 22 clocks
Therefore, the number of taps available is:
22 x 2 = 44 taps.
Multiplexing the four outputs gives a final output sample rate
of 8.192MSPS.
The impulse response is 44 taps at 16.384M or 22 output
samples (11 symbols at 4.096M).
The AGC loop filter output of channel 4 can be routed to
control the forward AGC gain control of all four channels.
This assures that the gains of the four back end sections are
the same. The gain error, however, is only computed from
every fourth output sample.
The back end processing sections of two or more ISL5216s
can be combined using the same polyphase approach, but
the AGC gain from one part cannot be shared with another
part (except via the μP interface), so polyphase filter using
multiple parts would typically usually use a fixed gain.
The filter sequencer is programmed via an instruction RAM
and several control registers. These are described below.
Instruction RAMs
The filter compute engine is controlled by a simple
sequencer supporting up to 32 steps. Each step can be a
filter or one of four sequence flow instructions—wait, jump
(conditional or unconditional), load loop counter, or NOP.
There are 128 bits per instruction word with each word
consisting of condition code selects, FIR parameters and
data routing controls. Not all of the instruction word bits are
used for all instruction types. The actual sequencer
instruction is only 9 bits. The rest of the bits are used for filter
parameters or for the loop counter preload. Each sequence
step is loaded by the microprocessor in four 32-bit writes.
The mapping of the bit fields for the instruction types is
shown in the instruction bit field table that follows. These FIR
instruction words can be generated using software tools
provided with the ISL5216 evaluation board.
When the filter is reset, the instruction pointer is set to 31
(the last instruction step). The read and write pointers are
initialized on reset, so a reset must be done when the
channel is initialized or restarted.
A fixed offset can be added to the starting read address of
one of the filters in the program. This function is provided to
offset the data reads of the filters in a polyphase filter bank;
all filters in the bank will write the same data to the same
RAM location. To offset the computations the RAM read
address is offset. See IWA = *00Bh for details.
The instruction word bits (127:0) are assigned to memory
words as follows:
31:0 to destination C C C C 0 0 0 1 0 x x x x x 0 0
63:32 to destination C C C C 0 0 0 1 0 x x x x x 0 1
95:64 to destination C C C C 0 0 0 1 0 x x x x x 1 0
127:96 to destination C C C C 0 0 0 1 0 x x x x x 1 1
where CCCC is the channel number and xxxxx is the
instruction sequence step number (0–31 decimal). Note the
μPHold bit in the filter compute engine control register
(IWA = *00Ah) must be set for the microprocessor to read
from or write to the instruction or coefficient RAMs.
17
FN6013.3
July 13, 2007