ISL5216_07 Datasheet, PDF (27/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
Table 1 details the phase and magnitude weighting for the 16
bits output from the PDC.
TABLE 1. MAG/PHASE BIT WEIGHTING
BIT
MAGNITUDE
PHASE (^o)
23 (MSB)
2²
180
22
2¹
90
21
2⁰
45
20
2^-1
22.5
19
2^-2
11.25
18
2^-3
5.625
17
2^-4
2.8125
16
2^-5
1.40625
15
2^-6
0.703125
14
2^-7
0.3515625
13
2^-8
0.17578125
12
2^-9
0.087890625
11
2^-10
0.043945312
10
2^-11
0.021972656
9
2^-12
0.010986328
8
2^-13
0.005483164
7
2^-14
0.002741582
6
2^-15
0.001370791
5
2^-16
0.0006853955
4
2^-17
0.00034269775
3
2^-18
0.00017134887
2
2^-19
0.00008567444
1
2^-20
0.00004283722
0 (LSB)
2^-21
0.00002141861
The magnitude and phase computation requires 17 clocks
for full precision. At the end of the 17 clocks, the magnitude
and phase are latched into a register to be held for the next
stage, either the output formatter or frequency discriminator.
If a new input sample arrives before the end of the 17 cycles,
the results of the computations up until that time, are
latched. This latching means that an increase in speed
causes only a decrease in accuracy. Table 2 details the
exact accuracy that can be obtained with a fixed number of
clock cycles up to the maximum of 17. The input magnitude
and phase errors induced by normal SNR values will almost
always be worse than the Cartesian to Polar conversion.
TABLE 2. MAG/PHASE ACCURACY vs CLOCK CYCLES
CLOCKS
MAGNITUDE
ERROR
(% f_S)
PHASE
ERROR
(°)†
PHASE
ERROR
(% f_S)
6
0.065
3.5
2
7
0.016
1.8
1
8
0.004
0.9
0.5
9
<0.004
0.45
0.25
10
<0.004
0.22
0.12
11
<0.004
0.11
0.062
12
<0.004
0.056
0.03
13
<0.004
0.028
0.016
14
<0.004
0.014
0.008
15
<0.004
0.007
0.004
16
<0.004
0.0035
0.002
17
<0.004
0.00175
0.001
† Assumes ±180° = f_S.
27
FN6013.3
July 13, 2007