ISL5216_07 Datasheet, PDF (12/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
The integrator bit widths are 69, 62, 53, 44, and 34 for the
first^t through fifth stages, respectively, while the comb bit
widths are all 32. The integrators are sized for decimation
factors of up to 512 with five stages, 2048 with four stages,
32768 with three stages, and 65536 with one or two stages.
Higher decimations in the CIC should be avoided as they
will cause integrator overflow. In the ISL5216, the
integrators are slightly oversized to reduce the quantization
noise at each stage.
A CIC filter has a gain of R^N, where R is the decimation factor
and N is the number of stages. Because the CIC filter gain
can become very large with decimation, an attenuator is
provided ahead of the CIC to prevent overflow. The 24 bits of
sample data are placed on the low 24 bits of a 69 bit bus
(width of the first CIC integrator) for a gain of 2^-45. A 48 bit
barrel shifter then provides a gain of 2⁰ to 2⁴⁷ inclusive
before passing the data to the CIC. The overall gain in the
pre-CIC attenuator can therefore be programmed to be any
one of 48 values from 2^-45 to 4, inclusive (see IWA=*004,
bits 19:14). This shift factor is adjusted to keep the total
barrel shifter and CIC filter gain between 0.5 and 1.0. The
equation which should be used to compute the necessary
shift factor is:
Shift Factor = 45 - Ceiling(log₂(R^N)).
CIC barrel shifts of greater than 45 will cause MSB bits to be
lost. Most of the floating point modes on the ISL5216 make
use of the CIC barrel shifter for gain. This limits the
maximum usable decimation. In particular, shift factor minus
maximum exponent must be greater than or equal to zero.
Maximum exponent ranges from 0 to 1, 3, or 7 for 1, 2 and 3
exponent bits, representing up to 6, 18, or 42dB of gain,
respectively. See Floating Point Input Mode section for
details.
12
FN6013.3
July 13, 2007