ISL5216_07 Datasheet, PDF (22/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
BIT
POSITIONS
125:123
127:126
INSTRUCTION BIT FIELDS (Continued)
FUNCTION
Coefficient Memory
Block-to-Block Step
Reserved
(ADDRC) Usually set to 0.
125:123 Step size
0
0
1
1
2
2
3
4
4
8
5
16
6
32
7
64
Set to 0
DESCRIPTION
Basic Instruction Set Examples
1. Wait for number of input samples > threshold
127:9 = 0
8:0 = 001
0000,0000,0000,0001h
2. Jump unconditional
127:9 = 0
8:0 = 1JJJJJ111b
example: jump to step 0= 0000,0000,0000,0107h
3. Jump RSCO (jump on resampler NCO carry output)
127:9 = 0
8:0 = 1JJJJJ101b
example: jump RSCO, step 0= 0000,0000,0000,0105h
4. Jump RSCO (jump on no resampler NCO carry output)
127:9 = 0
8:0 = 1JJJJJ100b
example: jump RSCO, step 0 = 0000,0000,0000,0104h
5. NOP single clock
127:9 = 0
8:0 = 010000000b
NOP1 = 0000,0000,0000,0080h
6. Load Loop Counter
127:21 = 0
20:9 = Loop counter preload (tested against 0)
8:0 = 010000100b
example: LdLpCntr 14 = 0000,0000,0000,1C84h
Single FIR Basic Program
This is the basic program for a single FIR. This program
applies to decimation filters (including DECx1) that are
symmetric or asymmetric (but not complex). The FIR output
is routed through path A with the AGC enabled.
0 - WAIT FOR ENOUGH SAMPLES
0000 0000 0000 0000 0000 0000 0000 0000 127:96
0000 0000 0000 0000 0000 0000 0000 0000 95:64
0000 0000 0000 0000 0000 0000 0000 0000 64:32
0000 0000 0000 0000 0000 0000 0000 0001 31:0
1 - FIR
0000 0001 0101 1111 1111 100R RRRR RRRR 127:96
00TT TTTT TTTD DDDD DDDD 0000 0000 0111 95:64
0000 1000 0000 0000 0000 1010 0000 0000 63:32
0000 1011 0000 0000 0FFF FFF0 1100 1000 31:0
2 - JUMP TO STEP 0
0000 0000 0000 0000 0000 0000 0000 0000 127:96
0000 0000 0000 0000 0000 0000 0000 0000 95:64
0000 0000 0000 0000 0000 0000 0000 0000 64:32
0000 0000 0000 0000 0000 0001 0000 0111 31:0
Four bit fields must be filled in:
F - filter type (this example applies to types 1-5)
D - decimation (also loaded into wait threshold)
T - number of taps minus 1
R - clocks/calculation (=floor((taps+1)/2) for symmetric, = taps for asymmetric)
The rest of the instruction RAM would typically be filled with NOP instructions:
0000 0000 0000 0000 0000 0000 0000 0000 127:96
0000 0000 0000 0000 0000 0000 0000 0000 95:64
0000 0000 0000 0000 0000 0000 0000 0000 64:32
0000 0000 0000 0000 0000 0000 1000 0000 31:0
00000000h
00000000h
00000000h
00000001h
015FF---h
-----007h
08000A00h
0B00--C8h
00000000h
00000000h
00000000h
00000107h
00000000h
00000000h
00000000h
00000080h
22
FN6013.3
July 13, 2007