ISL5216_07 Datasheet, PDF (20/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
BIT
POSITIONS
28:18
31:29
41:32
44:42
52:45
62:53
INSTRUCTION BIT FIELDS (Continued)
FUNCTION
Destination
Round Select
Data Memory
Block Start
Data Memory
Block Size
Data Memory
Block-to-Block Step
Coefficient Memory
Block Start
DESCRIPTION
Destination Field Bit Mapping
28
27
26
25
24 23 22 21 20 19 18
AGCLFGN AGCLF Path1 Path0 OS FB F4 F3 F2 F1 F0
AGCLFGN AGC loop gain select. Only applies to Path 1.
Loop gain 0 or 1 if AGCLF bit is set. Set to 0 (1 is a test mode for future chips).
AGCLF
AGC loop filter enable. Only applies to Path 1. The AGC loop is updated with the magnitude
of this sample (Path(1:0) = 01).
Path(1:0) Back End Data Routing Path Selection. (see Back End Data Routing figure)
00 Route output back to filter compute engine input to another FIR in the filter chain.
01 Route output thru the FIFO and AGC to outputs I1 and Q1.
10 Route output to I2 and Q2, bypassing the FIFO and AGC. This path
also routes to next channel FIR input.
11 Route output thru the FIFO and AGC to outputs I2 and Q2.
OS
Enable output strobe. Setting this bit generates a data ready signal when the data reaches
the output section and starts the serial output sequence (paths 1, 2, 3). If OS is not set,
there will be no output to the outside world from this channel, for that output calculation, but
the data will be loaded into its output holding register (OS would not be set when routing the
data to another back end when cascading channels).
FB
Feedback data path. When set, the magnitude and dphi/dt from the cartesian-to-polar coor-
dinate converter block are routed to the filter compute engine input (magnitude goes to the
I input and dphi/dt goes to the Q input). Provided for discriminator filtering.
F(4:0)
Filter select. For data recirculated to the input of the FIR processor by path 0 or from the
cartesian to polar coordinate converter output, these bits tell which filter sequencer step
gets it as an input.
31:29
Round Select (Add rounding bit at specified location).
000
2^-24, use this code when downshifting is not used.
001
2^-23
010
2^-22
011
2^-21
100
2^-20
101
2^-19
110
2^-18
111
no rounding.
Provided for use with the coefficient down-shift bits.
Memory block base address, 0-1023, 0-383 are valid for the ISL5216.
44:42
Block Size.
0
8
1
16
2
32
3
64
4
128
5
256
6
512
7
1024
(modulo addressing is used).
0-255, usually equal to the decimation factor for the FIR in this instruction.
Memory base address of coefficients, 0-1023, 0-511 are valid on the ISL5216.
20
FN6013.3
July 13, 2007