ISL68134_16 Datasheet, PDF (4/50 Pages) Intersil Corporation – Digital Dual Output, 7-Phase Configurable PWM

ISL68134
Functional Pin Descriptions Refer to Table 4 on page 19 for design layout considerations.
PIN NUMBER PIN NAME
DESCRIPTION
4, 3, 2, 1
PWM[3:0] Pulse width modulation outputs. Connect these pins to the PWM input pins of 3.3V logic compatible Intersil smart power
stages, driver IC(s) or power stages.
5
AVS_CLK AVSBus clock input pin. Connect to ground if not used.
6
AVS_SDA AVSBus data output pin. Leave open if not used.
7
AVS_MDA AVSBus data input pin. Connect to ground if not used.
8
AVS_VDDIO AVSBus reference voltage input pin. Leave open if not used.
9, 10, 38, 39,
40
DNC Do not connect any signals to these pins.
11
EN0 Input pin used for enable control of Output 0. Active high. Connect to ground if not used.
12
EN1 Input pin used for enable control of Output 1. Active high. Connect to ground if not used.
13
TWARN Thermal warning flag. This open-drain output will be pulled low in the event of a sensed over-temperature at TMON pins
without disabling the regulators. Maximum pull-up voltage is V_CC.
14
PG0 Open-drain power-good indicators for Output 0. Maximum pull-up voltage is V_CC.
15
PG1 Open-drain power-good indicators for Output 1. Maximum pull-up voltage is V_CC.
16
SCL Serial clock signal pin for SMBus interface. Maximum pull-up voltage is V_CC.
17
SDA Serial data signal pin for SMBus interface. Maximum pull-up voltage is V_CC.
18
SALRT Serial alert signal pin for SMBus interface. Maximum pull-up voltage is V_CC.
19
CONFIG Configuration ID selection pin. See Table 3 on page 16 for more details.
20
VINSEN Input voltage sense pin. Connect to VIN through a resistor divider (typically 40.2k/10k) with a 10nF decoupling capacitor.
21
VSEN1 Positive differential voltage sense input for Output 1. Connect to positive remote sensing point. Connect to ground if not
used.
22
RGND1 Negative differential voltage sense input for Output 1. Connect to negative remote sensing point. Connect to ground if not
used.
23, 25, 27, 29 CSRTN[3:0] The CS and CSRTN pins are current sense inputs to individual phase differential amplifiers. Unused phases should have
their respective current sense inputs grounded. The ISL68134 supports smart power stage, DCR and resistor sensing.
24, 26, 28, 30 CS[3:0] _{Connection details depend on current sense method chosen.}
31
RGND0 Negative differential voltage sense input for Output 0. Connect to negative remote sensing point. Connect to ground if not
used.
32
VSEN0 Positive differential voltage sense input for Output 0. Connect to positive remote sensing point. Connect to ground if not
used.
33
TMON0 Input pin for external temperature measurement at Output 0. Supports diode based temperature sensing as well as smart
power stage sensing. Refer to “Temperature Compensation” on page 14 for more information.
34
TMON1 Input pin for external temperature measurement at Output 1. Supports diode based temperature sensing as well as smart
power stage sensing. Refer to “Temperature Compensation” on page 14 for more information.
35
VCC Chip primary bias input. Connect this pin directly to a +3.3V supply with a high quality MLCC bypass capacitor.
36
VCCS Internally generated 1.2V LDO logic supply from VCC. Decouple with 4.7µF or greater MLCC (X5R or better).
37
SA PMBus™ Address selection pin. See Table 2 on page 12 for more details.
EPAD
GND Package pad serves as GND return for all chip functions. Connect directly to system GND plane with multiple thermal vias.
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FN8817.0
September 28, 2016