ISL68134_16 Datasheet, PDF (15/50 Pages) Intersil Corporation – Digital Dual Output, 7-Phase Configurable PWM

ISL68134
IPHASE#
DCR
V_OUT
CSRTNx
CURRENT
SENSE
CSx
TEMPERATURE
COMPENSATION
DCR_CORR
IPHASE#
TMONx
Vbe
VCCS
IC
T_C
k_SLOPE
T_OFFSET
TO TELEMETRY
T_SENSE
FIGURE 14. BLOCK DIAGRAM OF TEMPERATURE COMPENSATION
In the physical PCB design, the temperature sense diode (BJT) is
placed close to the inductor of the phase that is never dropped
during automatic phase drop operation. Additionally, a filter
capacitor no larger than 500pF should be added near the IC
between each TMON pin and VCCS. This is shown in Figure 15 on
page 15.
TMON1
IC
VCCS
TMON0
OPTIONAL AUXILIARY
TEMPERATURE SENSE
SW1
L1
SW2 SW3
L2
L3
OPTIONAL AUXILIARY
TEMPERATURE SENSE
SW0
L0
OUT1
OUT0
FIGURE 15. RECOMMENDED PLACEMENT OF BJT
Lossless Input Current and Power Sensing
Input current telemetry is provided via an input current
synthesizer. By utilizing the IC’s ability to precisely determine its
operational conditions, input current can be synthesized to a high
degree of accuracy without the need for a lossy sense resistor.
Fine-tuning of offset and gain are provided for in the GUI. Note
that input current sense fine-tuning must be done after output
current sense setup is finalized. With a precise knowledge of
input current and voltage, input power may be computed.
Input current and power telemetry is accessed via a PMBus™ and
easily monitored in the PowerNavigator™ GUI. V_IN is monitored
directly by the VINSEN pin through a 1:5 resistor divider as shown
in Figure 16.
VIN
40.2k
IC
VINSEN
10nF
10k
ADC
FIGURE 16. INPUT VOLTAGE SENSE CONFIGURATION
Voltage Regulation
Output voltage is sensed through the remote sense differential
amplifier and digitized. From this point, the regulation loop is
entirely digital. Traditional PID controls are utilized in conjunction
with several enhanced methods to compensate the voltage
regulation loop and tune the transient response.
Current Feedback
Current feedback in a voltage regulator is often utilized to ease
the stability design of the voltage feedback path. Additionally,
many microprocessors require the voltage regulator to have a
controlled output resistance (known as load line or droop
regulation) and this is accomplished utilizing current feedback.
For applications requiring droop regulation, the designer simply
specifies the output resistance desired using the
PowerNavigator™ GUI.
Current feedback stability benefits are available for rails that do
not specify droop regulation such as system agent. For these
applications, the designer may enable AC current feedback in the
GUI. With this configuration, the DC output voltage will be steady
regardless of load current.
Power-On Reset (POR)
Initialization of the ISL68134 begins after V_CC crosses its rising
POR threshold. When POR conditions are met, the internal 1.2V
LDO is enabled and basic digital subsystem integrity checks
begin. During this process, the controller will load the selected
user configuration from NVM as indicated by the CONFIG pin
resistor value, read V_IN UVLO thresholds from memory and start
the telemetry subsystem. With telemetry enabled, V_IN may be
monitored to determine when it exceeds its user programmable
rising UVLO threshold. Once V_CC and V_IN satisfy their respective
voltage conditions, the controller is in its shutdown state. It will
transition to its active state and begin soft-start when the state of
EN0/EN1 command a start-up. While in shutdown mode, the
PWM outputs are held in a high-impedance state to assure the
drivers remain off.
Soft-Start Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for an output to ramp to its target value after the delay
period has expired. These features may be used as part of an
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FN8817.0
September 28, 2016