ISL78420_15 Datasheet, PDF (3/18 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
Pin Descriptions
10 LD
1
14 LD
14
SYMBOL
VDD
3
3
4
4
5
5
8
11
7
10
9
12
10
13
2 1, 2, 6,
7, 8
6
9
-
-
HB
HO
HS
PWM
EN
VSS
LO
NC
RDT
EPAD
DESCRIPTION
Analog input supply voltage and positive supply for lower gate driver. Decouple this pin to ground with a 4.7µF
or larger high frequency ceramic capacitor to VSS. A 0.1µF ceramic decoupling capacitor placed close to VDD
and VSS pin is recommended.
High-side bootstrap supply voltage for upper gate driver referenced to HS. Connect the bootstrap capacitor to
this pin and HS.
High-side output driver connected to gate of high-side NMOS FET.
High-side gate driver reference node. Connect to source of high-side NMOS FET. Connect bootstrap capacitor
to this pin and HB.
Tri-level PWM input. Logic high drives HO high and LO low. Logic low drives HO low and LO high. In mid-level
state both outputs are driven low.
Output enable pin. When EN is low, HO = LO = 0. An internal 210kΩ pull-down resistor places EN in the low
state when the pin is left floating.
Analog supply ground. Decouple this pin to VDD with a 4.7µF or larger capacitor.
Low-side output driver connected to gate of low-side NMOS FET.
No Connect. This pin is isolated from all other pins. May optionally be connected to VSS.
A resistor connected between this pin and VSS adds dead time by adding delay time between the falling edge
of LO to rising edge of HO and falling edge of HO to rising edge of LO.
The EPAD is electrically isolated. It is recommended that the EPAD be connected to the VSS plane for heat
removal.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL78420AVEZ (Note 4)
Not Recommended for New Designs
ISL78420ARTAZ
78420 AVEZ
78420 AZ
-40 to +125
-40 to +125
14 Ld HTSSOP
10 Ld 4x4 TDFN
M14.173B
L10.4x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78420. For more information on MSL please see tech brief TB363.
4. These packages meet compliance with 100V Conductor Spacing Guidelines per IPC-2221.
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FN8296.3
November 6, 2014