ISL78420_15 Datasheet, PDF (11/18 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
2. Current flowing through the resistor across the gate-to-source
of the high-side FET.
3. Gate current when the high-side FET is turned ON.
The boot capacitor is recharged through the boot diode internal
to the ISL78420 during the time the low-side FET turns on, taking
the HS pin to ground. The ISL78420's internal boot diode has a
typical dynamic impedance of 0.8Ω, which recharges the boot
capacitor quickly. The low dynamic impedance allows the
ISL78420 to drive the high frequency half-bridge, depending on
the boot capacitor value used.
The following parameters are required to calculate the value of
the boot capacitor for a specific amount of voltage droop. In this
example, the values used are arbitrary. They should be changed
to comply with the actual application.
V_DD = 12V
V_DD can be any value between 8V and 14V
V_HB = V_DD - 0.7V = V_HO High-side driver bias voltage (V_DD - boot diode
voltage) referenced to V_HS
Period = 1ms
This is the longest expected switching period
I_HB = 150µA
R_GS = 100kΩ
Ripple = 5%
Worst case high-side driver current when
xHO = high (this value is specified for
V_DD = 12V)
Gate-source resistor (usually not needed)
Discharge droop voltage on the boot capacitor
(larger droop is not recommended)
I_{gate_leak} = 100nA
Qgate at 80V = 80nC
From the FET vendor’s datasheet
From Figure 21
12
I_D = 33A
10
V_DS = 80V
V_DS = 50V
8
V_DS = 20V
6
4
2
0
0 10 20 30 40 50 60 70 80
Q_gate TOTAL GATE CHARGE (nC)
FIGURE 21. TYPICAL GATE CHARGE OF A POWER NMOS FET
The following equations calculate the total charge required for
one switching cycle of the high-side FET. These equations
assume that all of the parameters are constant during the period
duration. The error is insignificant if the ripple voltage allowed is
small (5% or less as specified above).
Q_C = Q_gate + Period  I_HB + V_HO  R_GS + I_{gate_leak}
(EQ. 1)
C_boot = Q_C  Ripple^VDD
(EQ. 2)
C_boot = 0.57F
If the gate-to-source resistor is removed (R_GS is usually not
needed) then:
C_boot = 0.38µF
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Input Capacitor
The input capacitor to the VDD pin serves two main purposes. It
provides AC decoupling and transient current for the dynamic
switching of the high and low-side gate drivers of the ISL78420.
The second and more critical function is to provide the gate
charge to the low-side driven FET while keeping the VDD voltage
ripple to a minimum, similar to the function of the boot capacitor.
Improper input capacitance may cause excessive ripple on VDD
that triggers the UVLO falling threshold (6.7V typical), disabling
the driver. The minimum input capacitance required for the low-
side gate charge while maintaining an allowed ripple on VDD is
calculated similarly as the boot capacitor described in the
previous section. To account for the increased current of I_DD vs
I_HB, it is recommended to have the input capacitance be at
minimum 10x of the boot capacitor value. In addition, a 0.1µF
capacitor in parallel is recommended for high frequency
decoupling. For optimal performance, place these capacitors
close to the VDD and VSS pins.
Dead-Time Delay
When the PWM input transitions high or low, it is necessary to
ensure that both bridge FETs are not on at the same time to
prevent shoot-through currents. The ISL78420 programmable
timers delay the rising edge of the high-side (HO) and low-side
(LO) gate drives so that both FETs are off before one of them is
turned on. The dead time delay on the rising edge of LO and HO is
programmable with a single resistor from the RDT pin to V_SS. The
dead time is adjustable from 35ns (R_RDT = 80kΩ) to 220ns
(R_RDT = 8kΩ). It is not recommended to use resistors beyond
these values. The dead time is set equal on both falling edges of
LO and HO. See “Timing Diagram” on page 6 for the definition of
dead time delay. See Figure 8 on page 7 for the programmed
dead time vs resistor value.
While the voltage of the PWM signal is within the boundaries of
the mid-level logic (1.6V to 3.4V typical), the HO and LO pins are
driven low (with respect to VSS for LO pin and with respect to HS
for HO pin). The actual delay time, as programmed by the R_RDT
resistor value, begins when the high or low logic threshold levels
at the PWM input are crossed. The time when the PWM input is
in the mid-level range is added to the programmed dead time.
This should be a consideration when selecting the R_RDT value for
a specific dead time.
FN8296.3
November 6, 2014