ISL78420_15 Datasheet, PDF (13/18 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
HB
HO
HS
LO
VSS
CBOOT
RHS
-
+
-
+
INDUCTIVE
LOAD
FIGURE 24. RESISTOR AND DIODE NEGATIVE TRANSIENT CLAMP
The value of R_HS is determined by how much average current in
the clamping diode is acceptable. Current in the low-side FET
flows through the body diode during dead time resulting with a
negative voltage on HS that is typically about -1.5V. When the
low-side FET is turned on, the current through the body diode is
shunted away into the channel and the conduction voltage from
source-to-drain is typically much less than the conduction voltage
through the body diode. Consequently, significant current will
flow in the clamping diode only during the dead time. Because
the dead time is much less than the on time of the low-side FET,
the resulting average current in the clamping diode is very low.
The value of R_HS is then chosen to limit the peak current in the
clamping diode and usually just a few ohms is necessary.
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because the HS node is floating up toward the bridge bias
voltage. The Absolute Max voltage rating for the HS node does
need to be observed when the positive transient occurs.
The maximum rating for V_HB - V_HS = 14V must also not be
overlooked. When a negative transient, Vneg, is present on the
HS pin, the voltage differential across HB and HS will approach
VDD + Vneg. If the transient duration is short compared to the
charging time constant of the boot diode and boot capacitor, the
voltage across HB and HS is not significantly affected. However,
another source of negative voltage on the HS pin may increase
the boot capacitor voltage for a longer duration. During dead
time, current is flowing from the source-to-drain of the low-side
FET body diode. Depending on the size of the FET and the
amplitude of the reverse current, the voltage across the diode
can be as high as -1.5V and much higher during a load fault.
Because this negative voltage has little impedance, the boot
capacitor can charge to a voltage greater than VDD (for example
VDD + 1.5V). It may be necessary to either clamp the voltage as
described in Figures 23 and 24 and/or keep the dead time as
short as possible.
Power Dissipation
The power dissipation of the ISL78420 is dominated by the gate
charge required by the driven bridge FETs and the switching
frequency. The internal bias and boot diode also contribute to the
total dissipation but these losses are usually less significant
compared to the gate charge losses.
The calculation of the power dissipation of the ISL78420 is
approximated by the following equations:
GATE POWER (FOR THE HO AND LO OUTPUTS)
P_gate = Q_gateH + Q_gateL  Freq  VDD
where
(EQ. 3)
Q_gateH and Q_gateL is the total gate charge of the high-side and
low-side bridge FET respectively. VDD is the bias to the ISL78420
and Freq is the switching frequency.
BOOT DIODE DISSIPATION
I_{diode_avg} = Q_gate  Freq
(EQ. 4)
P_diode = I_{diode_avg}  0.7V
(EQ. 5)
Where 0.7V is the diode conduction voltage. Equations 4 and 5
represent the boot diode conduction loss from recharging the
boot capacitor during the refresh cycle. The average current is
proportional to the total charge delivered to the high-side NFET
and the switching frequency.
BIAS CURRENT
P_bias = I_bias  VDD
(EQ. 6)
where I_bias is the internal bias current of the ISL78420 at the
switching frequency (see Figures 3 and 4).
TOTAL POWER DISSIPATION
P_total = P_gate + P_diode + P_bias
JUNCTION OPERATING TEMPERATURE
T_J = P_total x _JA + T_A
where T_J is the junction temperature at the operating ambient
temperature, T_A, in the vicinity of the part.
T_J = P_total x _JC + T_PCB
where T_J is the junction temperature with the operating
temperature of the PCB, T_PCB, as measured where the EPAD is
soldered.
Submit Document Feedback ₁₃
FN8296.3
November 6, 2014