ISL78420_15 Datasheet, PDF(12/18 Page) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

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ISL78420_15 Datasheet, PDF (12/18 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

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ISL78420

8V TO 14V

ISL78420

VDD

PWM*

PWM

CONTROLLER

PWM

RDT

DRIVER

CBOOT

100V MAX

DRIVER

VSS

ISL78420

NOTE: The PWM signal from the controller

must be inverted for this active clamp

forward topology.

FIGURE 22. TYPICAL ACTIVE CLAMP FORWARD APPLICATION

Typical Application Circuit

Depending on the application, the switching speed of the bridge

FETs can be reduced by adding series connected resistors

between the HO output and the FET gate. Gate-Source resistors

are recommended on the low-side FETs to prevent unexpected

turn-on of the bridge should the bridge voltage be applied before

VDD. Gate-source resistors on the high-side FETs are not usually

required if low-side gate-source resistors are used. If relatively

low value gate-source resistors are used on the high-side FETs, be

aware that a larger value for the boot capacitor may be required.

solutions by themselves may not be sufficient. Figure 23

illustrates a simple method for clamping the negative transient.

Two series connected, fast 1 amp PN junction diodes are

connected between HS and VSS as shown. It is important that

these diodes be placed as close as possible to the HS and VSS

pins to minimize the parasitic inductance of this current path

between the two pins. Two diodes in series are required because

they are in parallel with the body diode of the low-side FET. If only

one diode is used for the clamp, it will conduct some of the

negative load current that is flowing in the body diode of the

low-side FET.

Transients on HS Node

An important operating condition that is occasionally overlooked

by designers is the negative transient on the HS pin that can

occur when the high-side bridge FET turns off. The maximum

transient allowed on the HS pin is -5V but it is wise to minimize

the amplitude to lower levels. This transient is the result of the

parasitic inductance of the low-side drain-source conductor on

the PCB. Even the parasitic inductance of the low-side FET

contributes to this transient.

When the high-side bridge FET turns off (see Figure 23), because

of the load inductive characteristics, the current that was flowing

in the high-side FET (blue) must rapidly commutate to flow

through the low-side FET (red). The amplitude of the negative

transient impressed on the HS node is (L*di/dt) where L is the

total parasitic inductance of the low-side FET drain-source path

and di/dt is the rate at which the high-side FET is turned off. With

the increasing power levels of power supplies and motors,

clamping this transient becomes significant for the proper

operation of the ISL78420.

In the event that the negative transient exceeds -5V, there are

several ways of reducing the negative amplitude of this transient.

If the bridge FETs are turned off more slowly to reduce di/dt, the

amplitude will be reduced but at the expense of more switching

losses in the FETs. Careful PCB design will also reduce the value

of the parasitic inductance. However, in extreme cases, these two

CBOOT

VSS

INDUCTIVE

LOAD

FIGURE 23. TWO CLAMPING DIODES TO SUPPRESS NEGATIVE

TRANSIENTS

An alternative to the two series connected diodes is one diode

and a resistor, (see Figure 24). In this case, it is necessary to limit

the current in the diode with a small value resistor, RHS,

connected between the phase node of the 1/2 bridge and the HS

pin. Observe that RHS is effectively in series with the HO output

and serves as a peak current limiting gate resistor on HO.

Submit Document Feedback 12

FN8296.3

November 6, 2014

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