ISL78420_15 Datasheet, PDF (10/18 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
Functional Description
Gate Drive for NMOS Half-Bridge
The ISL78420 is a NMOS FET driver for up to 100V half-bridge
configurations. In a half-bridge configuration the low-side FET
source is connected to ground while the low-side FET drain and
the high-side FET source are connected together to form the
phase or switching node. The drain of the high-side FET is
connected to the high voltage power supply.
The gate of the low-side FET requires a ground referenced drive
signal to switch on and off. The signal needs to be above the gate
threshold VGS of the FET. The gate drive of the high-side FET is
more challenging and is what the ISL78420 is designed for. The
high-side FET source is the phase node, which switches between
ground and the high voltage supply connected to the high-side
FET drain. The gate voltage needs to be above the source voltage
by V_GS to turn on (the source can be as high as 100V). A
bootstrap circuit is implemented to generate a bias voltage
above the voltage seen at the phase node to drive the gate of the
high-side FET.
Key properties of a half-bridge gate driver are:
1. Gate drive signals needs to be sufficiently higher than the V_GS
specified in MOSFET datasheets for proper operation. For 60V
to 100V NMOS FETs the gate threshold is in the range of 2V to
4V. For switching operation, the V_GS is typically specified in a
range of 8V to 12V.
2. Gate drive signal needs to provide sufficient current to charge
and discharge the dynamic gate capacitance of power
MOSFETs in the target switching frequencies up to 1MHz. For
60V to 100V NMOS FETs, the typical gate charge can be as
high as 80nC.
Functional Overview
The ISL78420 is a 100V, 2A high frequency half-bridge driver
designed to deliver the fast gate charge needed to switch
half-bridge configured NMOS FETs. The ISL78420 features a
tri-level logic input to control the high- and low-side gate driver
using only a single input pin. Typically, bridge drivers have
independent inputs to add dead-time control. The ISL78420 also
features a dead-time control allowing the user to program dead
time from a range of 35ns to 220ns with a single resistor to
ground.
A unique feature of the ISL78420 is the PWM pin’s tri-level logic
input. It allows control of the high-side and low-side drivers with a
single pin. When the PWM input is at logic high, the high-side
bridge FET is turned on and the low-side FET is off. When the
input is at logic low, the low-side bridge FET is turned on and the
high-side FET is turned off. When the input voltage is in tri-level
state, both the high and low-side bridge FETs are turned off. This
driver is designed to work in conjunction with the ISL78220,
“6-Phase Interleaved Boost PWM Controller with Light Load
Efficiency Enhancement” and with the ISL78225 “4-Phase
Interleaved Boost PWM Controller with Light Load Efficiency
Enhancement”. The enable pin (EN) when low turns both bridge
FETs off. The EN input is used when the interfacing controller
does not utilize a tri-level output. Both PWM and EN logic inputs
are V_DD tolerant.
The ISL78420 high-side driver bias is established by the internal
boot diode and the external boot capacitor connected between
the HB and HS pins. The charge on the boot capacitor is provided
by the internal boot diode that is connected from VDD to HB
(referred to as boot refresh). The current path to charge the boot
capacitor occurs when the low-side bridge FET is on, which takes
the phase node (HS pin) to ground. The charge current is limited
in amplitude by the internal resistance of the boot diode and the
low-side FET r_DS(ON). Assuming that the on time of the low-side
FET is sufficiently long to fully charge the boot capacitor, the boot
voltage on the HB pin (V_HB) will charge to VDD minus the boot
diode drop and the on-voltage of the low-side bridge FET.
When the PWM input transitions high, the high-side bridge FET is
driven on after the low-side FET is turned off. The HS node is
connected to the source of the high-side FET and the HS node will
rise almost to the level of the bridge voltage V_BRIDGE (minus the
on-voltage drop across the high-side FET). The boot capacitor
voltage is referenced to the source voltage of the high-side FET so
the V_HB voltage is approximately VDD volts above the HS node
and the boot diode is reversed biased by V_BRIDGE. Because the
high-side driver circuit is referenced to the HS node, the HO
output is now approximately V_HB + V_BRIDGE above ground. More
importantly the HO gate drive is approximately VDD above the HS
node to provide the proper V_GS to turn on the high-side FET.
During the low-to-high transition of the HS node, the boot
capacitor supplies the necessary charge current to fully turn on
the high-side FET gate. After the gate is fully charged, the boot
capacitor voltage continues to provide bias to the high-side gate
to keep the FET on. The stored charge of the boot capacitor must
be substantially larger than the required gate charge of the
high-side FET and the bias current of the high-side driver
otherwise the boot voltage will sag excessively. If the boot
capacitor value is too small for the required on-time of the
high-side FET, causing the boot voltage to drop below the
high-side bias HB pin UVLO falling threshold (6.3V typical), the
high-side driver is disabled resulting in undesireable operation.
See “Selecting the Boot Capacitor Value” on page 10 for
choosing the proper capacitor value.
Application Information
Selecting the Boot Capacitor Value
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the high-side driven
FET without causing the boot voltage to sag excessively. As good
practice, the boot capacitor should have a total charge that is
10x to 20x the gate charge of the power FET to achieve a 5% to
10% drop in voltage after the charge has been transferred from
the boot capacitor to the gate capacitance. The high-side driver
bias voltage is VDD - VF where VF is the voltage drop of the boot
diode. If the boot voltage (HB - HS) is allowed to drop below the
HB UVLO falling threshold (6.3V typical) this will disable the
high-side driver.
The boot capacitor is discharged by three means:
1. The bias current of the high-side gate driver.
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FN8296.3
November 6, 2014