ISL78420_15 Datasheet, PDF (14/18 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
High Voltage Conductor Spacing
The HTSSOP package adheres to IPC-2221 guidelines for high
voltage conductor spacing of external component leads. The
required pin-to-pin spacing for 100V conductors is 0.5mm for
nonconformal coat PCB boards. For the ISL78420 14 Ld HTSSOP
package, the high voltage pins are separated from the low
voltage pins across the 4.4mm wide package. While the HB, HO
and HS pins are grouped together and can swing from 0V to
114V, under normal operation the maximum differential voltage
across these pins is limited by the VDD supply (14V Max
Operating).
PC Board Layout
The AC performance of the ISL78420 depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance
from the ISL78420:
• Understand how power currents flow. The high amplitude di/dt
currents of the bridge FETs will induce significant voltage
transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Avoid paralleling high di/dt traces with low level signal lines.
High di/dt will induce currents in the low level signal lines.
• When practical, minimize impedances in low level signal
circuits; the noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Core gaps in these structures are especially bad for
emitting flux.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines.
• The use of low inductance components such as chip resistors
and chip capacitors is recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductors. To be effective, these capacitors must also have the
shortest possible lead lengths. If vias are used, connect several
paralleled vias to reduce the inductance of the vias.
• It may be necessary to add resistance to dampen resonating
parasitic circuits. In PCB designs with long leads on the LO and
HO outputs, it may be necessary to add series gate resistors on
the bridge FETs to dampen the oscillations.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for the PWM
control circuits.
• Avoid having a signal ground plane under a high dv/dt circuit.
This will inject high di/dt currents into the signal ground paths.
• Do power dissipation and voltage drop calculations of the
power traces. Most PCB/CAD programs have built in tools for
calculation of trace resistance.
• Large power components (Power FETs, Electrolytic capacitors,
power resistors, etc.) will have internal parasitic inductance,
which cannot be eliminated. This must be accounted for in the
PCB layout and circuit design.
• If you simulate your circuits, consider including parasitic
components.
EPAD Design Considerations
The thermal pad of the ISL78420 is electrically isolated. Its
primary function is to provide heat sinking for the IC. It is
recommended to tie the EPAD to V_SS (GND).
Figure 25 is an example of how to use vias to remove heat from
the IC substrate. Depending on the amount of power dissipated by
the ISL78420, it may be necessary to connect the EPAD to one or
more ground plane layers. A via array, within the area of the EPAD,
will conduct heat from the EPAD to the ground plane on the bottom
layer. If inner PCB layers are available, it would also be desirable
to connect these additional layers with the plated-through vias.
The number of vias and the size of the GND planes required for
adequate heat-sinking is determined by the power dissipated by
the ISL78420, the air flow, and the maximum temperature of the
air around the IC.
It is important that the vias have a low thermal resistance for
efficient heat transfer. Do not use “thermal relief” patterns to
connect the vias.
EPAD GND
VDD
PLANE
LO
HB
VSS
HO
PWM
HS
TOP
NC
LAYER
EN
RDT
EPAD GND
VDD PLANE
LO
This plane is
HB
connected to
HS and is under
all high side
HO
driver circuits
HS
NC
VSS
PWM
EN
BOTTOM
LAYER
RDT
FIGURE 25. RECOMMENDED PCB HEATSINK
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FN8296.3
November 6, 2014