ISL78420_15 Datasheet, PDF (16/18 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision. (Continued)
DATE
REVISION
CHANGE
November 6, 2014
(continued)
FN8296.3
(continued)
Page 5 and Page 6
1.EN Input Low Level Threshold
a.T = 25C specifications changed from MIN = 1.4; TYP = 1.8 to MIN = 1.8; TYP = 2.5
b.Full Temperature specifications changed from MIN = 1.2 to MIN = 1.8
2.EN Input High Level Threshold
a.T = 25C specifications changed from TYP = 1.8; MAX = 2.2 to TYP = 2.8; MAX = 4.
b.Full Temperature specification change from MAX = 2.4 to MAX = 4.1
3.EN Pull-Up Resistance changed to EN Pull-Down Resistor. Resistance value unchanged. This is to correct
previous datasheet revision error. Not a functional change to the die.
4.Under Voltage Protection VDD Rising Threshold
a.MAX limit changed from 8.1V to 8.0V
5.Bootstrap Diode
a.Low Current Forward Voltage: Changed test condition from 100mA to 100µA. This is to correct previous
datasheet revision error. Not a functional change to the test.
b.Dynamic Resistance: Test condition clarified. Added formula to calculate dynamic resistance at 50mA and
100mA diode current. This is to correct previous datasheet revision error. Not a functional change to the test.
6.Switching Specification Test Condition: Changed RDT = 0kΩ to RDT = 8kΩ or 80kΩ.
7.Added Dead Time Delay Matching Specifications for RDT at 8kΩ and 80kΩ.
Page 7 to Page 9
1.Updated Figures Figures 3 through 6 for clarity.
2. Figure 7 (High Level Output Voltage vs Temp) and Figure 8 (Low Level Output Voltage vs Temp) moved to
Figures 11 and 12 and updated for clarity.
3. Figure 9 (UVLO Rising Threshold) and Figure 10 (UVLO Hysteresis) moved to Figures 15 and 16 and revised for
clarity.
4. Figure 11 (Propagation Delay vs Temp) moved to Figure 7 and updated for clarity.
5. Figure 12 (Delay Matching vs Temp) removed.
6. Figure 13 (Peak Pull-up Current) and Figure 14 (Peak Pull-down Current) updated for clarity.
7. Figure 15 (Quiescent Current vs Voltage) moved to Figures 19 and 20 and updated for clarity.
8.Figure 16 moved to Figure 10 and updated for clarity.
9.Removed Figure 17 (VHS Voltage to VDD Voltage Derating)
10.Added additional Typical Performance Curves for Output Impedance vs Temp and PWM Threshold Voltages
Page 10 to Page 12
1.Added to Applications Section: Gate Drive for NMOS Half Bridge
2.Added to Applications Section: Input Capacitor
3.Added to Application Section: Dead Time Delay
4.Added to Application Section: High Voltage Conductor Spacing
5.Application Section: Transient On HS Node updated with new content
6. Equation 1 updated to fix format error.
7. Equation 3 updated to fix error.
January 24, 2014
FN8296.2
Page 14
- 2nd line of the disclaimer changed from:
"Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted"
to:
"Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality
systems as noted"
Updated "Products" verbiage to "About Intersil" verbiage
September 24, 2012 FN8296.1 Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
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FN8296.3
November 6, 2014