D2-926XX_14 Datasheet, PDF (28/38 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-926xx
Reset
D2-926xx has one reset input: the nRESET pin. The nRESET input
pin (active low, non-reset high) is effectively a power-on system
reset. All internal state logic is initialized by nRESET. While reset
is active the system is held in the reset condition which is defined
as all internal reset signals being active, the crystal oscillator is
running, and the PLL disabled. At the de-assertion of nRESET, the
chip will capture the boot mode selection from the IRQ[D:A] pins
and begin the boot process.
The nRSTOUT pin is an active low open drain reset output. This
pin drives low from the internal power-on-reset generator, 3.3V
brownout detector going active, or from 1.8V brownout detector
going active. This output should be used to initiate a system
reset, and to also connect to the nRESET pin to initiate a DAE
reset upon brownout event detection.
Booting and Boot Modes
D2-926xx includes a fully-programmable DSP with internal boot
ROM. The boot ROM’s primary function is to download a
second-stage boot image from one of several possible sources.
The system requires external firmware to boot the internal DSP.
Internal ROM within the DAE-3 initiates the boot process to read
the boot records and firmware, to load into the internal DAE-3
memory. The boot ROM code is designed to handle both
encrypted and non-encrypted boot images from any of the boot
modes shown in Table 2.
The specific boot mode is selected based on the state of the
IRQD, IRQC, IRQB, and IRQA pins at the time of reset
de-assertion. The mode is selected by a hardware pull-up or
pull-down connection to each of the four boot mode (IRQ[D:A])
pins. (Modes not listed are reserved.)
Control Interfaces
I²C 2-WIRE INTERFACE
The D2-926xx family ICs have two separate I²C 2-Wire
compatible ports. Port 1 is used as the external controller
interface, and Port 0 is used for booting from an external
EEPROMs or compatible chips. Both I²C interfaces are
multi-master capable.
SERIAL PERIPHERAL INTERFACE (SPI™)
The Serial Peripheral Interface (SPI) is provides an alternate boot
source interface such as an SPI Flash. The SPI port is used only
for boot operation. Register control of the system firmware is not
implemented through the SPI interface.
MODE IRQ[D:A]
0
0000
1
0001
2
0010
3-F
-
DAE M/S
Slave
Master
Master
-
TABLE 2. BOOT MODES
XTALI RANGE
N/A
24.576MHz
INTERFACE SPEED
DESCRIPTION
per Master
I²C port 1 slave to external master, boot @ address 88
400kb/s
I²C port 0 master to I²C EEPROM slave
24.576MHz
1.53MHz
SPI port master to SPI Flash slave
-
-
Reserved
28
FN6787.2
July 12, 2012