D2-926XX_14 Datasheet, PDF (13/38 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-926xx
Pin Description, DAE-3 (128-Pin)
PIN
VOLTAGE DRIVE
NAME
LEVEL STRENGTH
PIN (Note 16) TYPE (V)
(mA)
DESCRIPTION
1
SC20 I/O
3.3
8
Serial Audio Interface 2, I²S0 SCLK
2
SRD2 I/O
3.3
4
Serial Audio Interface 2, I²S0 SDIN
3
SC21 I/O
3.3
8
Serial Audio Interface 2, I²S0 LRCK
4
SCK2 I/O
3.3
8
Serial Audio Interface 2, I²S1 SCLK
5
STD2 I/O
3.3
8
Serial Audio Interface 2, I²S1 SDIN
6
SC22 I/O
3.3
4
Serial Audio Interface 2, I²S1 LRCK
7
MCLK
O
3.3
16
I²S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset and
is enabled by firmware assignment.
8
SCK3 I/O
3.3
8
Serial Audio Interface 3, I²S3 SCLK
9
STD3 I/O
3.3
8
Serial Audio Interface 3, I²S3 SDIN
10 SC32 I/O
3.3
8
Serial Audio Interface 3, I²S3 LRCK
11 SC30 I/O
3.3
8
Serial Audio Interface 3, I²S2 SCLK
12 SC31 I/O
3.3
8
Serial Audio Interface 3, I²S2 LRCK
13 SRD3 I/O
3.3
4
Serial Audio Interface 3, I²S2 SDIN
14 STD0 I/O
3.3
8
Serial Audio Interface 0, I²S SDAT0
15 SCK0 I/O
3.3
8
Serial Audio Interface 0, I²S LRCK0
16 CVDD
P
3.3
Core power, 1.8V
17 CVDD
P
3.3
Core power, 1.8V
18 CGND
P
3.3
Core ground
19 CGND
P
3.3
Core ground
20 RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
21 RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
22 SRD0 I/O
3.3
4
Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
23 SC00 I/O
3.3
24 SC01 I/O
3.3
25 SC02 I/O
3.3
8
Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
8
Serial Audio Interface 0, I²S SDAT1
8
Serial Audio Interface 0, I²S LRCK1
26
SCK
I/O
3.3
4
SPI clock I/O with hysteresis input.
27
TIO1
I/O
3.3
16
Timer I/O port 1. Operation and assignment is controlled by firmware. Leave unconnected when
not in use.
28 MISO I/O
3.3
4
SPI master input, slave output data signal.
29
MOSI
I/O
3.3
4
SPI master output, slave input data signal.
30 GPIO7 I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
31 GPIO3 I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
32 GPIO2 I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
33 GPIO4 I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
13
FN6787.2
July 12, 2012