D2-926XX_14 Datasheet, PDF (14/38 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-926xx
Pin Description, DAE-3 (128-Pin) (Continued)
PIN
VOLTAGE DRIVE
NAME
LEVEL STRENGTH
PIN (Note 16) TYPE (V)
(mA)
DESCRIPTION
34 GPIO5 I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
35 GPIO6 I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
36 SDA1 I/O
3.3
8 - OD
Two-Wire Serial data port 1. Bidirectional signal used by both the master and slave controllers for
data transport.
37 SCL1 I/O
3.3
8 - OD
Two-Wire Serial clock port 1. Bidirectional signal is used by both the master and slave controllers
for clock signaling.
38 PROTECT9 I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
39 SPDIFRX1 I
3.3
S/PDIF Digital audio data input 1
40 SPDIFRX0 I
3.3
S/PDIF Digital audio data input 0
41 SPDIFTX O
3.3
4
S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent upon
firmware, driving stereo output up to 192kHz.)
42
TEST
I
3.3
Factory test use only. Must be tied low.
43 IRQA
I
3.3
Interrupt request port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
44 IRQB
I
3.3
Interrupt request port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
45 IRQC
I
3.3
Interrupt request port C, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
46 IRQD
I
3.3
Interrupt request port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
47
TIO2
I/O
3.3
16
Timer I/O port 2. Operation and assignment is controlled by firmware. Leave unconnected when
not in use.
48 CVDD
P
3.3
Core power, 1.8V
49 CVDD
P
3.3
Core power, 1.8V
50 CGND
P
3.3
Core ground
51 CGND
P
3.3
Core ground
52 RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
53 RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
54 PUMPHI I/O
3.3
16
Assignable I/O. Function and operation defined by firmware.
55 PUMPLO I/O
3.3
16
Assignable I/O. Function and operation defined by firmware.
56 PSSYNC I/O
3.3
16
Synchronizing output signal to switching power supply. (Operates under specification of firmware
and resets to high impedance inactive state when not used.)
57 PSTEMP I/O
3.3
4
Assignable I/O. Function and operation defined by firmware.
58 PSCURR I/O
3.3
4
Assignable I/O. Function and operation defined by firmware.
59 PWMSYNC I/O
3.3
16
PWM synchronization port. (Function and operation is defined by firmware.)
60 PROTECT3 I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
14
FN6787.2
July 12, 2012