D2-926XX_14 Datasheet, PDF (27/38 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-926xx
Amplifier Protection
The core firmware that operates the DAE-3 family devices
supports protection options to prevent damage from faults
present in class-D amplifier designs. This protection is also
effective against user-induced faults such as clipping, output
overload, or output shorts, including both shorted outputs or
short-to-ground faults.
Protection features and their details are firmware dependent.
The Audio Canvas III program provides selection for assignment
and use of certain protection methods, using the selections for
building the system firmware.
GRACEFUL OVERCURRENT AND SHORT CIRCUIT
Per-channel PWM protection is supported through individual
protection input pins. These PROTECT pins are primarily intended
for protecting the PWM powered output stages and operation is
firmware controlled. The protection input signal is typically
generated by sensing circuits within power stages and can
include sensing for detecting current, temperature, or voltage
fault conditions.
Overcurrent sensing requires a current sensor in the power
device to be protected, usually a powered PWM output. The
typical sensor asserts its fault signal that is routed to the
PROTECT pins of the DAE device.
The D2-926xx devices observe the overcurrent protection inputs
and provides graceful protection for the assigned output stages.
Hardware may be configured to provide immediate current
reduction, cycle-by-cycle output clipping, output signal control,
and output stage deactivation depending on the severity and
duration of high current events. The combination of hardware
features and firmware monitoring allows the system to
differentiate between an overcurrent situation or a more serious
short circuit condition, and supports the managed protection
within the DAE amplifier systems.
THERMAL PROTECTION
Temperature monitoring may be used to provide warning,
shutdown, or managed output level reduction to attempt to
reduce heating effects at high load power. Multiple thermal
protection methods are supported within the DAE family
firmware. User choice of method and operation is
programmable, using the Audio Canvas III software to configure
settings and options.
Hardware I/O Features
The DAE-3 and DAE-3HT provides programmable I/O pins used
for various hardware functions of the system design. Pin
functions are defined by the product firmware and configured
with the Audio Canvas III software.
GENERAL-PURPOSE I/O AND TIMERS
General Purpose I/O (GPIO) pins are available for system use
with the DAE-3 and are assignable by choice selection in the
Audio Canvas III software. The DAE-3 supports pins assignable to
various hardware features, while the DAE-3HT shares functions
of some of its available device pins providing feature choices in a
lower pin-count package.
Timers provides programmed I/O control of features that are
event or timing dependent. Their hardware pins are assigned to
system features, and operation is controlled through firmware.
Timer pins are configurable based on the features supported
within the system firmware. Choice and operation of their
assigned features is selected through the Audio Canvas III
software that builds the firmware for the specific system project.
POWER SUPPLY SYNCHRONIZATION
The PSSYNC pin provides a power supply synchronization signal
for switching power supplies. This synchronizing of power supply
switching with the PWM switching rate eliminates audio output
tones generated if the switching power supply is not locked to the
amplifier switching.
Firmware settings configure PSSYNC to the desired frequency
needed by the system switching regulator. The Audio Canvas III
software supports selection of use and frequency of this output.
Clocks And PLL
The PLL block operation is completely managed by the system
firmware. The clock generation contains a low jitter PLL critical
for low noise PWM output and a precise master clock source for
the ADC, sample rate conversion, and the audio data paths.
The PLL block includes a low noise crystal oscillator, clock
multipliers clock generation for all internal device timing, PWM
engine timing, and clock reference for use with assignable clock
outputs that include MCLK and PSSYNC outputs.
The system clock is provided by the crystal oscillator, using either
a fundamental mode crystal or a clock input to the XTALI pin. If
the clock input is used, it must be a 1.8V signal level. The input
signal on the XTALI pin is analog buffered and driven onto the
OSCOUT pin for use in driving the XTALI input of other D2-926xx
controllers, for supporting synchronous timing if multiple DAE
devices are used in a single application.
Reset and Initialization
The D2-926xx must be reset after power-up to begin proper
operation. In normal system hardware configurations, the reset
occurs automatically via the reset hardware circuitry. The chip
contains power rail sensors, brownout detectors, on the 3.3V and
1.8V power supplies. These brownout sensors will assert and hold
an internal Power-on Reset which will disable the device until the
power supplies are at a safe level for the DSP to start. These same
brownout sensors will detect a power supply voltage droop while
the system is active and provide a safe amplifier shutdown.
Power Sequencing
The CVDD and RVDD (including PWMVDD) supplies should be
brought up together to avoid high current transients that could
fold back a power supply regulator. The ADCVDD and PLLVDD
may be brought up separately. Best practice would be for all
supplies to feed from regulators with a common power source.
Typically this can be achieved by using a single 5V power source
and regulating the 3.3V and 1.8V supplies from that 5V source.
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FN6787.2
July 12, 2012