D2-926XX_14 Datasheet, PDF (17/38 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-926xx
Pin Description, DAE-3 (128-Pin) (Continued)
PIN
VOLTAGE DRIVE
NAME
LEVEL STRENGTH
PIN (Note 16) TYPE (V)
(mA)
DESCRIPTION
117 SC10 I/O
3.3
8
Serial Audio Interface 1, data (Assignment by firmware control.)
118 STD1 I/O
3.3
8
Serial Audio Interface 1, SDAT2
119 SCK1 I/O
3.3
8
Serial Audio Interface 1, SCK
120 SRD1 I/O
3.3
4
Serial Audio Interface 1, data (Assignment by firmware control.)
121 nRSTOUT O
3.3
16 - OD Active low open drain reset output. Pin drives low from POR generator, 3.3V brownout detector
going active, or from 1.8V brownout detector going active. This output should be used to initiate a
system reset to the nRESET pin upon brownout event detection.
122 nRESET
I
3.3
Active low reset input with hysteresis. Activates system level reset when pulled low, initializing all
internal logic and program operations. System latches boot mode selection of the IRQ input pins
on the rising edge.
123 TIO0
I/O
3.3
16
Timer I/O port 0. Operation and assignment is controlled by firmware. Leave unconnected when
not in use.
124 PROTECT1 I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
125 PROTECT0 I/O
3.3
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel
assignment is defined by firmware.)
126 GPIO0 I/O
3.3
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and
assignment is defined by product application's firmware.)
127 SDA0 I/O
3.3
8 - OD
Two-Wire Serial data port 0. Bidirectional signal used by both the master and slave controllers for
data transport.
128 SCL0 I/O
3.3
8 - OD
Two-Wire Serial clock port 0. Bidirectional signal is used by both the master and slave controllers
for clock signaling.
NOTES:
16. Unless otherwise specified, all pin names are active high. Those that are active low have an “n” prefix.
17. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins
to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and
PWMGND pins are also internally connected and are to be tied together.
17
FN6787.2
July 12, 2012