D2-926XX_14 Datasheet, PDF (16/38 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-926xx
Pin Description, DAE-3 (128-Pin) (Continued)
PIN
VOLTAGE DRIVE
NAME
LEVEL STRENGTH
PIN (Note 16) TYPE (V)
(mA)
DESCRIPTION
87 PWM6 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
88 PWM5 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
89 PWM4 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
90 PWMVDD P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected
to RVDD.
91 PWMGND P
3.3
PWM output pin ground. Internally connected to RGND.
92 PWM3 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
93 PWM2 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
94 PWM1 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
95 PWM0 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
96 PWMVDD P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to
RVDD.
97 OSCOUT P
1.8
Analog oscillator output to slave D2-926xx devices. OSCOUT drives a buffered version of the
crystal oscillator signal from the XTALI pin.
98 PLLAGND P
1.8
PLL Analog ground
99 PLLTESTB O
1.8
Factory test use only. Must be tied low.
100 PLLTESTA O
1.8
Factory test use only. Must be tied low.
101 XTALI
P
1.8
Crystal oscillator analog input port. An external clock source would be driven into the this port. In
multi-D2-926xx systems, the OSCOUT from the master D2-926xx would drive the XTALI pin.
102 XTALO
P
1.8
Crystal oscillator analog output port. When using an external clock source, this pin must be open.
XTALO does not have a drive strength specification.
103 PLLAVDD P
1.8
PLL Analog power, 1.8V
104 ADCVDD P
3.3
Analog power for internal ADC, 3.3V
105 AIN1
I
3.3
Analog input 1 to internal ADC
106 ADCREF O
3.3
Analog voltage reference output. Must be de-coupled to analog ground with 1µF capacitor.
107 AIN0
I
3.3
Analog input 0 to internal ADC
108 ADCGND P
3.3
Analog ground for internal ADC
109 nTRST
I
3.3
Factory test only. Must be tied high at all times.
110 nCS
I/O
3.3
4
SPI slave select I/O.
111 RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
112 RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
113 CGND
P
3.3
Core ground
114 CVDD
P
3.3
Core power, 1.8V
115 SC12 I/O
3.3
8
Serial Audio Interface 1, LRCK
116 SC11 I/O
3.3
8
Serial Audio Interface 1, SDAT3
16
FN6787.2
July 12, 2012