D2-926XX_14 Datasheet, PDF (18/38 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-926xx
Pin Description DAE-3HT (72-Pin)
PIN
VOLTAGE DRIVE
NAME
LEVEL STRENGTH
PIN (Note 16) TYPE (V)
(mA)
DESCRIPTION
1 SCLK3 In
3.3
(SC20)
8
Bit clock, I²S port 3, audio input channels 5-6. (I²S port 3 is 1 of 3 input-only ports, providing
channels 5-6 input audio content.)
2
SDIN3
In
3.3
(SRD2)
4
Audio data, I²S port 3, audio input channels 5-6 (I²S port 3 is 1 of 3 input-only ports, providing
channels 5-6 input audio content.)
3 LRCK3 In
3.3
(SC21)
8
L/R clock, I²S port 3, audio input channels 5-6 (I²S port 3 is 1 of 3 input-only ports, providing
channels 5-6 input audio content.)
4 SCLK4 In
3.3
(SCK2)
8
Bit clock, I²S port 4, audio input channels 7-8, or audio output channels 1-2. (I²S port 4 is either
an I²S input port, or and I²S output port. Selection of input or output is defined by firmware. When
used as input, port 4 provides channel 7-8 input audio content. When used as an output, port 4
provides the 2 channels of I²S output audio.)
5 SDIO4 I/O
3.3
(STD2)
8
Audio data, I²S port 4, input channels 7-8, or output channels 1-2. (I²S port 4 is either an I²S input
port, or and I²S output port. Selection of input or output is defined by firmware. When used as
input, port 4 provides channel 7-8 input audio content. When used as an output, port 4 provides
the 2 channels of I²S output audio.)
6 LRCK4 In
3.3
(SC22)
4
L/R clock, I²S port 4, audio input channels 7-8, or audio output channels 1-2. (I²S port 4 is either
an I²S input port, or and I²S output port. Selection of input or output is defined by firmware. When
used as input, port 4 provides channel 7-8 input audio content. When used as an output, port 4
provides the 2 channels of I²S output audio.)
7 SCLK12 In
3.3
(SCK3)
8
Bit clock, I²S ports 1 & 2, audio input channels 1-4 (I²S ports 1 & 2 are 2 of the 3 input-only ports,
providing channels 1-4 input audio content.)
8
SDIN2
In
3.3
(STD3)
8
Audio data, I²S port 2, audio input channels 3-4 (I²S ports 1 & 2 are 2 of the 3 input-only ports,
providing channels 1-4 input audio content.)
9 LRCK12 In
3.3
(SC32)
8
L/R clock, I²S ports 1 & 2, audio input channels 1-4 (I²S ports 1 & 2 are 2 of the 3 input-only ports,
providing channels 1-4 input audio content.)
10 SDIN1
In
3.3
(SRD3)
8
Audio data, I²S port 1, audio input channels 1-2 (I²S ports 1 & 2 are 2 of the 3 input-only ports,
providing channels 1-4 input audio content.)
11 CVDD
P
3.3
Core power, 1.8V
12 CGND
G
3.3
Core ground
13 RGND
G
3.3
Digital pad ring ground. Internally connected to PWMGND.
14 RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
15
SCK
I/O
3.3
4
SPI clock I/O with hysteresis input.
16 TIO1/NTC I/O
3.3
16
Timer I/O port 1, or assignable NTC temperature sensing common I/O. Operation and assignment
is controlled by firmware. Leave unconnected when not in use.
17 MISO I/O
3.3
4
SPI master input, slave output data signal.
18 MOSI I/O
3.3
19 SDA1 I/O
3.3
20 SCL1 I/O
3.3
4
8 - OD
8 - OD
SPI master output, slave input data signal.
Two-Wire Serial (I²C) data port 1. Primary control interface data signal used for device boot and
control. Bidirectional port for both master and slave controllers operation.
Two-Wire Serial (I²C) clock port 1. Primary control interface clock signal used for device boot and
control. Bidirectional port for both master and slave controllers operation.
21 SPDIFRX In
3.3
S/PDIF Digital audio data input
22 SPDIFTX O
3.3
S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent upon
firmware, driving stereo output up to 192kHz.)
23
TEST
In
3.3
Factory test use only. Must be tied low.
24 IRQA
In
3.3
Interrupt request port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to
ground and High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
18
FN6787.2
July 12, 2012