D2-926XX_14 Datasheet, PDF (20/38 Pages) Intersil Corporation – Intelligent Digital Amplifier and Sound Processor

D2-926xx
Pin Description DAE-3HT (72-Pin) (Continued)
PIN
VOLTAGE DRIVE
NAME
LEVEL STRENGTH
PIN (Note 16) TYPE (V)
(mA)
DESCRIPTION
47 PWM6
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
48 PWM5
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
49 PWM4
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
50 PWMGND O
3.3
PWM output pin power ground
51 PWM3
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
52 PWM2
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
53 PWM1
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
54 PWM0
O
3.3
8 or 16 PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by
firmware.)
55 PWMVDD P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to
RVDD.
56 PLLAGND G
1.8
PLL Analog ground
57 XTALI
In
1.8
58 XTALO
O
1.8
59 PLLAVDD P
1.8
Crystal oscillator analog input port. When using an external clock source, the external clock is
driven into the this port.
Crystal oscillator analog output port. When using an external clock source, this pin must be open.
XTALO does not have a drive strength specification.
PLL Analog power, 1.8V
60
nSS
O
3.3
4
SPI slave select I/O.
61 RVDD
P
3.3
62 RGND
G
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers. Internally connected to PWMVDD.
Digital pad ring ground. Internally connected to PWMGND.
63 CGND
G
3.3
Core ground
64 CVDD
P
3.3
Core power, 1.8V
65 SCK1 I/O
3.3
/MCLK
66 nRSTOUT O
3.3
67 nRESET In
3.3
68
TIO0
I/O
3.3
/PSSYNC
8
16 - OD
16
Assignable general purpose I/O, or MCLK output. Operation and assignment is controlled by
firmware. Assigns as default output for MCLK when enabled through firmware.
Active low open drain reset output. Pin drives low from POR generator, 3.3V brownout detector
going active, or from 1.8V brownout detector going active. This output should be used to initiate a
system reset to the nRESET pin upon brownout event detection.
Active low reset input with hysteresis. Activates system level reset when pulled low, initializing all
internal logic and program operations. System latches boot mode selection of the IRQ input pins
on the rising edge.
Timer I/O port 0, or power supply sync output. Operation and assignment is controlled by
firmware. Leave unconnected when not in use.
20
FN6787.2
July 12, 2012