ISL12022M_10 Datasheet, PDF (27/31 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12022M
SIGNALS ^S
S
FROM THE ^T IDENTIFICATION
T _{IDENTIFICATION}
S
MASTER ^A
BYTE WITH
ADDRESS
A _{BYTE WITH}
A
A
T
R
R/W = 0
T
BYTE
R
R/W = 1
T
C
C
O
K
K
P
SIGNAL AT
SDA
11011110
A
SIGNALS FROM
C
THE SLAVE
K
11011111
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
LAST READ
DATA BYTE
FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
Figure 21 shows a suggested layout for the ISL12022M
device. The following main precautions should be
followed:
• Do not run the serial bus lines or any high speed logic
lines in the vicinity of pins 1 and 20, or under the
package. These logic level lines can induce noise in
the oscillator circuit, causing misclocking.
Measuring Oscillator Accuracy
The best way to analyze the ISL12022M frequency
accuracy is to set the IRQ/F_OUT pin for a specific
frequency, and look at the output of that pin on a high
accuracy frequency counter (at least 7 digits accuracy).
Note that the IRQ/F_OUT is an drain output and will
require a pull-up resistor.
• Add a ground trace around the device with one end
terminated at the chip ground. This guard ring will
provide termination for emitted noise in the vicinity of
the RTC device
• Be sure to ground pins 6 and 15 as well as pin 8 as
these all insure the integrity of the device ground
• Add a 0.1µF decoupling capacitor at the device V_DD
pin, especially when using the 32.768kHz F_OUT
function.
Using the 1.0Hz output frequency is the most convenient
as the ppm error is expressed in Equation 6:
ppm error = F_OUT – 1 • 1e6
(EQ. 6)
Other frequencies may be used for measurement but the
error calculation becomes more complex. Use the F_OUT
output and a frequency counter for the most accurate
results. Also, when the proper layout guidelines above
are observed, the oscillator should start-up in most
circuits in less than one second.
The best way to run clock lines around the RTC is to stay
outside of the ground ring by at least a few millimeters.
Also, use the V_BAT and V_DD as guard ring lines as well,
they can isolate clock lines from the oscillator section. In
addition, if the IRQ/F_OUT pin is used as a clock, it should
be routed away from the RTC device as well.
Temperature Compensation Operation
The ISL12022M temperature compensation feature
needs to be enabled by the user. This must be done in a
specific order as follows.
1. Read register 0Dh, the BETA register. This register
contains the 5-bit BETA trimmed value, which is
automatically loaded on initial power-up. Mask off
the 5 LSB’s of the value just read.
GROUND
RING
F_OUT
2. Bit 7 of the BETA register is the master enable
control for temperature sense operation. Set this to
“1” to allow continuous temperature frequency
correction. Frequency correction will then happen
every 60 seconds with V_DD applied.
3. Bits 5 and 6 of the BETA register control
temperature compensation in battery backup mode
(see Table 15). Set the values for the operation
desired.
SCL
4. Write back to register 0Dh making sure not to
change the 5 LSB values, and include the desired
SDA
compensation control bits.
FIGURE 21. SUGGESTED LAYOUT FOR THE
ISL12022M
Note that every time the BETA register is written with the
TSE bit = 1, a temperature compensation cycle is
instigated and a new correction value will be loaded into
the FATR/FDTR registers (if the temperature changed
since the last conversion).
Also note that registers 0Bh and 0Ch, the ITR0 and
ALPHA registers, are READ-ONLY, and cannot be written
to. Also the value for BETA is locked and cannot be
changed with a write. However, It is still a good idea to
do the bit masking when doing TSE bit changes.
27
FN6668.7
June 4, 2010