ISL12022M_10 Datasheet, PDF(13/31 Page) Intersil Corporation – Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

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ISL12022M_10 Datasheet, PDF (13/31 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

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ISL12022M

5. Time Stamp for VDD Status (5 bytes): Address 1Bh

to 1Fh.

6. Day Light Saving Time (8 bytes): 20h to 27h.

7. TEMP (2 bytes): 28h to 29h.

8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah,

2Bh

9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch

10. Crystal ALPHA at high temperature, ALPHA_H (1

byte): 2Dh

11. Scratch Pad (2 bytes): Address 2Eh and 2Fh

Write capability is allowable into the RTC registers (00h

to 06h) only when the WRTC bit (bit 6 of address 08h) is

set to â1â. A multi-byte read or write operation should be

limited to one section per operation for best RTC time

keeping performance.

A register can be read by performing a random read at

any address at any time. This returns the contents of

that register location. Additional registers are read by

performing a sequential read. For the RTC and Alarm

registers, the read instruction latches all clock registers

into a buffer, so an update of the clock does not change

the time being read. At the end of a read, the master

supplies a stop condition to end the operation and free

the bus. After a read, the address remains at the

previous address +1 so the user can execute a current

address read and continue reading the next register.

When the previous address is 2Fh, the next address will

wrap around to 00h.

It is not necessary to set the WRTC bit prior to writing

into the control and status, alarm, and user SRAM

registers.

TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS)

BIT

REG

ADDR. SECTION NAME

0 RANGE DEFAULT

00h

SC22

SC21

SC20

SC13

SC12

SC11

SC10 0 to 59

00h

01h

MN22

MN21

MN20

MN13

MN12

MN11

MN10 0 to 59

00h

02h

MIL

HR21

HR20

HR13

HR12

HR11

HR10 0 to 23

00h

03h

RTC

DT21

DT20

DT13

DT12

DT11

DT10 1 to 31

01h

04h

MO20

MO13

MO12

MO11

MO10 1 to 12

01h

05h

YR23

YR22

YR21

YR20

YR13

YR12

YR11

YR10 0 to 99

00h

06h

DW2

DW1

DW0

0 to 6

00h

07h

BUSY

OSCF DSTADJ

ALM

LVDD

LBAT85 LBAT75

RTCF

N/A

01h

08h

INT

ARST

WRTC

FOBATB

FO3

FO2

FO1

FO0

N/A

01h

09h

PWR_VDD CLRTS

VDDTrip2 VDDTrip1 VDDTrip0 N/A

00h

0Ah

PWR_VBAT D

RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0 N/A

00h

0Bh

CSR

ITRO

IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00

N/A

XXh

0Ch

ALPHA

ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0 N/A

XXh

0Dh

BETA

TSE

BTSE

BTSR

BETA4 BETA3 BETA2 BETA1 BETA0

N/A

XXh

0Eh

FATR

FFATR5 FATR4

FATR3

FATR2

FATR1

FATR0

N/A

00h

0Fh

FDTR

FDTR4 FDTR3 FDTR2 FDTR1 FDTR0

N/A

00h

10h

SCA0

ESCA0 SCA022 SCA021 SCA020 SCA013 SCA012 SCA011 SCA010 00 to 59

00h

11h

MNA0 EMNA0 MNA022 MNA021 MNA020 MNA013 MNA012 MNA011 MNA010 00 to 59

00h

12h

HRA0 EHRA0

HRA021 HRA020 HRA013 HRA012 HRA011 HRA010 0 to 23

00h

ALARM

13h

DTA0

EDTA0

DTA021 DTA020 DTA013 DTA012 DTA011 DTA010 01 to 31

00h

14h

MOA0 EMOA00

MOA020 MOA013 MOA012 MOA011 MOA010 01 to 12

00h

15h

DWA0 EDWA0

DWA02 DWA01 DWA00 0 to 6

00h

FN6668.7

June 4, 2010

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