ISL12022M_10 Datasheet, PDF (21/31 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12022M
registers. Any one alarm register, multiple registers, or
all registers can be enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
• Single Event Mode is enabled by setting the bit 7
on any of the Alarm registers (ESCA0... EDWA0) to
“1”, the IM bit to “0”, and disabling the frequency
output. This mode permits a one-time match
between the Alarm registers and the RTC registers.
Once this match occurs, the ALM bit is set to “1” and
the IRQ/F_OUT output will be pulled low and will
remain low until the ALM bit is reset. This can be
done manually or by using the auto-reset feature.
• Interrupt Mode is enabled by setting the bit 7 on
any of the Alarm registers (ESCA0... EDWA0) to “1”,
the IM bit to “1”, and disabling the frequency output.
The IRQ/F_OUT output will now be pulsed each time
an alarm occurs. This means that once the interrupt
mode alarm is set, it will continue to alarm for each
occurring match of the alarm and present time. This
mode is convenient for hourly or daily hardware
interrupts in microcontroller applications such as
security cameras or utility meter reading.
To clear a single event alarm, the ALM bit in the status
register must be set to “0” with a write. Note that if the
ARST bit is set to 1 (address 08h, bit 7), the ALM bit will
automatically be cleared when the status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
• Alarm set with single interrupt (IM = “0”)
• A single alarm will occur on January 1 at 11:30 a.m.
• Set Alarm registers as follows:
BIT
ALARM
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled
MNA0
1 0 1 1 0 0 0 0 B0h Minutes set to
30, enabled
HRA0
1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
DTA0
1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
MOA0
1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
DWA0
0 0 0 0 0 0 0 0 00h Day of week
disabled
After these registers are set, an alarm will be generated
when the RTC advances to exactly 11:30 a.m. on
January 1 (after seconds changes from 59 to 00) by
setting the ALM bit in the status register to “1” and also
bringing the IRQ/F_OUT output low.
Example 2
• Pulsed interrupt once per minute (IM = “1”)
• Interrupts at one minute intervals when the seconds
register is at 30 seconds.
• Set Alarm registers as follows:
ALARM
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
SCA0
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled
HRA0 0 0 0 0 0 0 0 0 00h Hours disabled
DTA0 0 0 0 0 0 0 0 0 00h Date disabled
MOA0 0 0 0 0 0 0 0 0 00h Month disabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled
Once the registers are set, the following waveform will be
seen at IRQ/F_OUT:
RTC AND ALARM REGISTERS ARE BOTH “30s”
60s
FIGURE 14. IRQ/F_OUT WAVEFORM
Note that the status register ALM bit will be set each time
the alarm is triggered, but does not need to be read or
cleared.
Time Stamp V_DD to Battery Registers
(TSV2B)
The TSV2B Register bytes are identical to the RTC
register bytes, except they do not extend beyond the
Month. The Time Stamp captures the FIRST V_DD to
Battery Voltage transition time, and will not update upon
subsequent events until cleared (only the first event is
captured before clearing). Set CLRTS = 1 to clear this
register (Add 09h, PWR_V_DD register).
Note that the time stamp registers are cleared to all “0”,
including the month and day, which is different from the
RTC and alarm registers (those registers default to 01h).
This is the indicator that no time stamping has occurred
since the last clear or initial power-up. Once a time
stamp occurs, there will be a non-zero time stamp.
Time Stamp Battery to V_DD Registers
(TSB2V)
The Time Stamp Battery to VDD Register bytes are
identical to the RTC register bytes, except they do not
extend beyond Month. The Time Stamp captures the
LAST transition of VBAT to VDD (only the last event of a
series of power-up/power-down events is retained). Set
CLRTS = 1 to clear this register (Add 09h, PWR_V_DD
register).
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FN6668.7
June 4, 2010