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ISL12022M_10 Datasheet, PDF (17/31 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving
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ISL12022M
Power Supply Control Register (PWR_VDD)
CLEAR TIME STAMP BIT (CLRTS)
ADDR 7 6 5 4 3
2
1
0
09h
CLRTS 0 0 0 0 VDDTrip2 VDDTrip1 VDDTrip0
This bit clears Time Stamp VDD to Battery (TSV2B) and
Time Stamp Battery to VDD Registers (TSB2V). The
default setting is 0 (CLRTS = 0) and the Enabled setting
is 1 (CLRTS = 1).
VDD BROWNOUT TRIP VOLTAGE BITS
(VDDTRIP<2:0>)
These bits set the trip level for the VDD alarm, indicating
that VDD has dropped below a preset level. In this event,
the LVDD bit in the Status Register is set to “1”. See
Table 6.
TABLE 6. VDD TRIP LEVELS
VDDTrip2
0
VDDTrip1
0
VDDTrip0
0
TRIP
VOLTAGE
(V)
2.295
0
0
1
2.550
0
1
0
2.805
0
1
1
3.060
1
0
0
4.250
1
0
1
4.675
Battery Voltage Trip Voltage Register
(PWR_VBAT)
This register controls the trip points for the two VBAT
alarms, with levels set to approximately 85% and 75% of
the nominal battery level.
TABLE 7.
ADDR 7
6
5
4
3
2
1
0
0Ah
D RESEALB VB85 VB85 VB85 VB75 VB75 VB75
Tp2 Tp1 Tp0 Tp2 Tp1 Tp0
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting the VBAT
pin from the internal circuitry. Setting this bit allows the
device to disconnect the battery and eliminate standby
current drain while the device is unused. Once VDD is
powered up, this bit is reset and the VBAT pin is then
connected to the internal circuitry.
The application for this bit involves placing the chip on a
board with a battery and testing the board. Once the
board is tested and ready to ship, it is desirable to
disconnect the battery to keep it fresh until the board or
unit is placed into final use. Setting RESEALB = “1”
initiates the battery disconnect, and after VDD power is
cycled down and up again, the RESEAL bit is cleared
to “0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP
<2:0>)
Three bits select the first alarm (85% of Nominal VBAT)
level for the battery voltage monitor. There are total of
7 levels that could be selected for the first alarm. Any of
the of levels could be selected as the first alarm with no
reference as to nominal Battery voltage level. See
Table 8.
TABLE 8. VB85T ALARM LEVEL
VB85Tp2
VB85Tp1
VB85Tp0
BATTERY ALARM
TRIP LEVEL
(V)
0
0
0
2.125
0
0
1
2.295
0
1
0
2.550
0
1
1
2.805
1
0
0
3.060
1
0
1
4.250
1
1
0
4.675
BATTERY LEVEL MONITOR TRIP BITS (VB75TP
<2:0>)
Three bits select the second alarm (75% of Nominal
VBAT) level for the battery voltage monitor. There are
total of 7 levels that could be selected for the second
alarm. Any of the of levels could be selected as the
second alarm with no reference as to nominal Battery
voltage level. See Table 9.
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS
(VB75TP <2:0>)
VB75Tp2
VB75Tp1
BATTERY ALARM
TRIP LEVEL
VB75Tp0
(V)
0
0
0
1.875
0
0
1
2.025
0
1
0
2.250
0
1
1
2.475
1
0
0
2.700
1
0
1
3.750
1
1
0
4.125
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room
temperature) of the crystal. Both Digital Trimming (DT)
and Analog Trimming (AT) methods are available. The
digital trimming uses clock pulse skipping and insertion
for frequency adjustment. Analog trimming uses load
capacitance adjustment to pull the oscillator frequency. A
range of +62.5ppm to -61.5ppm is possible with
combined digital and analog trimming.
Initial values for the ITR0 register are preset internally
and recalled to RAM registers on power-up. These
values are pre-set in device production and are
READ-ONLY. They cannot be overwritten by the
17
FN6668.7
June 4, 2010
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