ISL12022M_10 Datasheet, PDF (16/31 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12022M
Example - When the LBAT75 is Set to “1” in Battery
Mode:
The minute register changes to 30h when the device is in
battery mode, the LBAT75 is set to “1” the next time the
device switches back to Normal Mode.
Example - When the LBAT75 Remains at “0” in
Battery Mode:
If the device enters into battery mode after the minute
register reaches 49h and switches back to Normal Mode
before minute register reaches 50h, then the LBAT75 bit
will remain at “0” the next time the device switches
back to Normal Mode.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a
read only bit that is set by hardware (ISL12022M
internally) when the device powers up after having lost
all power (defined as V_DD = 0V and V_BAT = 0V). The bit
is set regardless of whether V_DD or V_BAT is applied first.
The loss of only one of the supplies does not set the RTCF
bit to “1”. The first valid write to the RTC section after a
complete power failure resets the RTCF bit to “0” (writing
one byte is sufficient).
Interrupt Control Register (INT)
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR 7
6
5
4
3210
08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM,
LVDD, LBAT85, and LBAT75 status bits only. When ARST
bit is set to “1”, these status bits are reset to “0” after a
valid read of the respective status register (with a valid
STOP condition). When the ARST is cleared to “0”, the
user must manually reset the ALM, LVDD, LBAT85, and
LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this
bit is “0”. Upon initialization or power-up, the WRTC must
be set to “1” to enable the RTC. Upon the completion of a
valid write (STOP), the RTC starts counting. The RTC
internal 1Hz signal is synchronized to the STOP condition
during a valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will
operate in the interrupt mode, where an active low pulse
width of 250ms will appear at the IRQ/F_OUT pin when
the RTC is triggered by the alarm, as defined by the
alarm registers (0Ch to 11h). When the IM bit is cleared
to “0”, the alarm will operate in standard mode, where
the IRQ/F_OUT pin will be set low until the ALM status bit
is cleared to “0”.
IM BIT
0
1
TABLE 4.
INTERRUPT/ALARM FREQUENCY
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By
Alarm
FREQUENCY OUTPUT AND INTERRUPT BIT
(FOBATB)
This bit enables/disables the IRQ/F_OUT pin during
battery backup mode (i.e. V_BAT power source active).
When the FOBATB is set to “1”, the IRQ/F_OUT pin is
disabled during battery backup mode. This means that
both the frequency output and alarm output functions
are disabled. When the FOBATB is cleared to “0”, the
IRQ/F_OUT pin is enabled during battery backup mode.
Note that the open drain IRQ/F_OUT pin will need a
pull-up to the battery voltage to operate in battery
backup mode.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function
and select the output frequency at the IRQ/F_OUT pin.
See Table 5 for frequency selection. Default for the
ISL12022M is
FO<3:0> = 1h, or 32.768kHz output (F_OUT is ON).
When the frequency mode is enabled, it will override
the alarm mode at the IRQ/F_OUT pin.
TABLE 5. FREQUENCY SELECTION OF IRQ/F_OUT PIN
FREQUENCY,
F_OUT
UNITS
0
Hz
FO3
0
FO2
0
FO1
0
FO0
0
32768
Hz
0
0
0
1
4096
Hz
0
0
1
0
1024
Hz
0
0
1
1
64
Hz
0
1
0
0
32
Hz
0
1
0
1
16
Hz
0
1
1
0
8
Hz
0
1
1
1
4
Hz
1
0
0
0
2
Hz
1
0
0
1
1
Hz
1
0
1
0
1/2
Hz
1
0
1
1
1/4
Hz
1
1
0
0
1/8
Hz
1
1
0
1
1/16
Hz
1
1
1
0
1/32
Hz
1
1
1
1
16
FN6668.7
June 4, 2010