ISL6264 Datasheet, PDF (21/24 Pages) Intersil Corporation – Two-Phase Core Controller for AMD Mobile Turion CPUs

ISL6264
even at light loads between the VSUM and VO' nodes. As a
rule of thumb we start with the voltage drop across the R_n
network, VN, to be 0.5-0.8 times VDCR_EQU. This ratio
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
The resultant NTC network resistor value is dependent on
the temperature and given by
R_n(T)
=
(_---R_{-----s---e---r--i--e---s----+-----}R_{----n----t--c---})_---⋅_---R_{-----p---a----r}
R_series + R_ntc + R_par
(EQ. 7)
For simplicity, the gain of Vn to the Vdcr_equ is defined by
G1, also dependent on the temperature of the NTC
thermistor.
G₁(T)
=
------------^R-----ⁿ---⁽---^T----⁾------------
R_n(T) + R_sequ
(EQ. 8)
DCR(T) = DCR_25C ⋅ (1 + 0.00393*(T-25))
(EQ. 9)
Therefore, the output of the droop amplifier divided by the
total load current can be expressed as follows:
R_droop
=
G₁
(
T
)
⋅
-^D----^C-----^R-----²---⁵-
2
⋅
(1
+
0.00393
*(T-25)
)
⋅
k_d
r
o
op
(EQ. 10)
where Rdroop is the realized load line slope and 0.00393 is
the temperature coefficient of the copper. To achieve the
droop value independent from the temperature of the
inductor, it is equivalently expressed by the following.
G₁(T) ⋅ (1 + 0.00393*(T-25)) ≅ G_{1t arg et}
(EQ. 11)
The non-inverting droop amplifier circuit has the gain
k_droopamp expressed as:
k_droopamp
=
1 + ^R-----^d---^r---^p---²-
R_drp1
(EQ. 12)
G_1target is the desired gain of Vn over I_OUT. DCR/2.
Therefore, the temperature characteristics of gain of Vn is
described by:
G₁(T)
=
-----------------¹----¹---^t--^a---^r--^g----^e---^t----------------
(1 + 0.00393*(T-25))
(EQ. 13)
For the G1 target = 0.76, the R_ntc = 10kΩ with b = 4300,
R_series = 2610kΩ, and R_par = 11kΩ, R_seqv = 1825Ω generates
a desired G1, close to the feature specified in Equation 20.
The actual G1 at +25°C is 0.769. For different G1 and NTC
thermistor preference, the design file to generate the proper
value of R_ntc, R_series, R_par, and R_seqv is provided by Intersil.
Then, the individual resistors from each phase to the VSUM
node, labeled R_S1 and R_S2 in Figure 31, are then given by
Equation 14.
Rs = 2 ⋅ R_seqv
(EQ. 14)
So, R_S = 3650Ω. Once we know the attenuation of the R_S and
R_n network, we can then determine the droop amplifier gain
required to achieve the load line. Setting Rdrp1 = 1k_1%,
then Rdrp2 is can be found using Equation 15:
R_drp2
=
⎛
⎝
----------²-----^â‹---^R-----^d---^r--^o---^o----^p----------
DCR ⋅ G1(25°C)
–
1_⎠⎞
⋅ R_drp1
(EQ. 15)
Droop Impedance (Rdroop) = 0.002 (V/A) as per the AMD
specification, DCR = 0.0008Ω typical for a 0.36µH inductor,
Rdrp1 = 1kΩ and the attenuation gain (G1) = 0.77, Rdrp2 is
then:
R_drp2
=
⎛
⎝
0^----.^-0^-2---0^--⋅-0^--R--8^--d--⋅^--r-0^-o---.^o-7^--p--6^---9^--
–
1_⎠⎞
⋅ 1kΩ
=
5.62 k Ω
(EQ. 16)
Note, we choose to ignore the R_O resistors because they do
not add significant error.
These designed values in R_n network are very sensitive to
layout and coupling factor of the NTC to the inductor. As only
one NTC is required in this application, this NTC should be
placed as close to the Channel 1 inductor as possible and
PCB traces sensing the inductor voltage should be go
directly to the inductor pads.
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This is fairly
easy and can be accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
Rdrp2 to obtain the appropriate load line slope.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
as much as possible to minimize engineering time.
The 2mV/A load line should be adjusted by Rdrp2 based on
maximum current, not based on small current steps like 10A,
as the droop gain might vary between each 10A steps.
Basically, if the max current is 40A, the required droop
voltage is 84mV. The user should have 40A load current on
and look for 84mV droop. If the drop voltage is less than
84mV, for example, 80mV. the new value will be calculated
by:
R_drp2
=
8_----4_----m_-----V_---
80mV
(
R_drp1
+
R_d
rp
2
)
–
R_dr
p1
(EQ. 17)
Do not let the mismatch get larger than 600Ω. To reduce the
mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate
factor. The appropriate factor in the example is
1404/853 = 1.65. In summary, the predicted load line with
the designed droop network parameters based on the
design tool is shown in Figure 33.
21
FN6359.1
October 16, 2006