ISL6264 Datasheet, PDF (19/24 Pages) Intersil Corporation – Two-Phase Core Controller for AMD Mobile Turion CPUs

ISL6264
Using a SLEWRATE of 4.2mV/µs, and the typical I₂ value,
given in the Electrical Specification table of 230µA, C_SOFT is:
C_SOFT ≡ (230µA) ⁄ (4.2)
(EQ. 3)
A choice of 0.047µF would guarantee a SLEWRATE of
3.7mV/µs is met for minimum I₃ value, given in the Electrical
Specification Table. This choice of C_SOFT will then control the
Start-Up slewrate as well. One should expect the output
voltage to slew to the VID value of 1.2V at a rate given by
Equation 4:
d_----V_---
dt
=
------^I--^S----^S-------
C_SOFT
=
-----⁴---³----^µ----^A------
0.047 µ F
=
0.9^mV ⁄ (µS)
(EQ. 4)
Selecting R_BIAS
To properly bias the ISL6264, a reference current is
established by placing a 147kΩ, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10A current source from which OCSET reference current
can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the R_BIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Start-up Operation - PGOOD
The internal timer allows PGOOD to go high approximately
7.6ms after Vout reaches the target VID voltage during the
start-up.
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
The VSEN and RTN pins of the ISL6264 are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are Vcc_sense and
Vss_sense respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode capacitor filters to analog ground on VSEN and RTN.
Whether to need these capacitors really depends on the
actual board layout and noise environment.
Due to the fact that the voltage feedback to the switching
regulator is sensed at the processor die, there exists the
potential of an over voltage due to an open circuited
feedback signal, should the regulator be operated without
the processor installed. Due to this fact, we recommend the
use of the Ropn1 and Ropn2 connected to VOUT and
ground (illustrated in Figure 31). These resistors will provide
voltage feedback in the event that the system is powered up
without a processor installed. These resistors may typically
range from 20Ω to 100Ω.
ISEN1
ISEN2
ISEN1
OC
ISEN2
10µA
-
+
INTERNAL TO
OCSET
VSUM
+
DROOP
-
DFB
R_OCSET
VO'
VSUM
I_phase1
RS
VSUM
ISL6264
+
S
+
VDIFF
0.018µF
1
+
-
DROOP
1
+
-
RTN
VSEN
VO'
0.018µF
10
R_opn1
to V_OUT
I_phase2
R_{OCSET VSUM}
RS
VO'
R_opn2
VCC_SENSE
VSS_SENSE
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
L₁
+ ^Vdcr1-
DCR
R_L1
C_L1
RO1
ISEN1
L₂
R_L2
ISEN2
VO'
DCR
+ ^Vdcr2-
RO2
C_L2
VO'
V_OUT
C_bulk
ESR
FIGURE 31. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
19
FN6359.1
October 16, 2006