ISL6264 Datasheet, PDF (17/24 Pages) Intersil Corporation – Two-Phase Core Controller for AMD Mobile Turion CPUs

ISL6264
mode, thus achieving the highest possible efficiency. In this
mode of operation, the lower FET will be configured to
automatically detect and prevent discharge current flowing
from the output capacitor through the inductors, and the
switching frequency will be proportionately reduced, thus
greatly reducing both conduction and switching losses.
Smooth mode transitions are facilitated by the R3
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms which robustly
maintain voltage-regulation for all control signal input
sequences and durations.
Mode-transition sequences will often occur in concert with
VID changes; therefore the timing of the mode transition of
ISL6264 has been carefully designed to work in concert with
VID changes. For example, transitions into single-phase
mode if PSI_L and VID toggles at the same time will be
delayed until the VID induced voltage ramp is complete, to
allow the associated output capacitor charging current is
shared by both inductor paths. While in single-phase
automatic-DCM mode with PSI_L = logic low, VID changes
will initiate an immediate return to two-phase CCM mode
during the VID transition. This ensures that both inductor
paths share the output capacitor charging current and are
fully active for the subsequent load current increases.
The controller contains internal counters which prevent
spurious control signal glitches from resulting in unwanted
mode transitions. Control signals of less than two switching
periods do not result in phase-idling. Signals of less than
seven switching periods do not result in implementation of
automatic-DCM mode.
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the
active-phase, and detects the idling-phase zero-current
condition. During transitions into automatic-DCM or
forced-CCM mode, the timing is carefully adjusted to eliminate
output voltage excursions. When a phase is added, the
current balance between phases is quickly restored.
Dynamic Operation
The ISL6264 responds to changes in VID command voltage
by slewing to new voltages with a dV/dt set by the SOFT
capacitor. The internal current source of 230µA is used to
charge or discharge the SOFT capacitor.
Intersil's R3 Technology™ has intrinsic voltage feed forward.
As a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6264 will transiently raise the
switching frequency so that response time is decreased and
current is shared by two channels.
Protection
The ISL6264 provides overcurrent, overvoltage, and
undervoltage protection as shown in Table 3.
Overcurrent protection is tied to the voltage droop which is
determined by the resistors selected as described in the
"Component Selection and Application" section on page 18.
After the load-line is set, the OCSET resistor can be selected
to detect overcurrent at any level of droop voltage. An
overcurrent fault will occur when the load current exceeds
the overcurrent setpoint voltage while the regulator is in a 2-
phase mode. While the regulator is in a 1-phase mode of
operation, the overcurrent setpoint is automatically reduced
by half. For overcurrents less than 2.5 times the OCSET
level, the over-load condition must exist for 120µs in order to
trip the OC fault latch.
For overloads exceeding 2.5 times the set level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection due to hard shorts.
In addition, excessive phase unbalance, for example, due to
gate driver failure, will be detected in two-phase operation
and the controller will be shut-down after one millisecond's
detection of the excessive phase current unbalance. The
phase unbalance is detected by the voltage on the ISEN
pins if the difference is greater than 9mV.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6264
FAULT DUATION
PRIOR TO
PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurrent fault
< 2µs
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
Overvoltage fault (1.8V)
immediately
Low-side FET on until Vcore < 0.85V, then PWMs three- VDD toggle
state, PGOOD latched low (OV-1.8V always)
Overvoltage fault (+200mV)
1ms
ISL6264 still tries to regulate Vcore, PGOOD latched low VR_ON toggle or VDD toggle
Undervoltage fault (-300mV)
1ms
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
Unbalance fault (9mV)
1ms
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
17
FN6359.1
October 16, 2006