ISL6264 Datasheet, PDF (15/24 Pages) Intersil Corporation – Two-Phase Core Controller for AMD Mobile Turion CPUs

ISL6264
Theory of Operation
The ISL6264 is a two-phase regulator providing the power to
AMD Mobile CPUs such as Turion CPUs and includes
integrated gate drivers for reduced system cost and board
area. The regulator provides optimum steady-state and
transient performance for microprocessor core applications
up to 50A. System efficiency is enhanced by idling a phase
at low-current and implementing automatic DCM-mode
operation when PSI_L is asserted to logic low.
The heart of the ISL6264 is the R3 Technology™, Intersil's
Robust Ripple Regulator modulator. The R3 modulator
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. The ISL6264 modulator internally synthesizes
an analog of the inductor ripple current and uses hysteretic
comparators on those signals to establish PWM pulse
widths. Operating on these large-amplitude, noise-free
synthesized signals allows the ISL6264 to achieve lower
output ripple and lower phase jitter than either conventional
hysteretic or fixed frequency PWM controllers. Unlike
conventional hysteretic converters, the ISL6264 has an error
amplifier that allows the controller to maintain a 0.5% voltage
regulation accuracy throughout the VID range from 0.75V to
1.55V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients results in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. Transient load current is inherently shared
between active phases due to the use of a common
hysteretic window voltage. Individual average phase
voltages are monitored and controlled to equally share the
static current among the active phases.
Start-up Timing
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
100µs later, SOFT and VOUT begin ramping toward the final
VID voltage. At startup, the regulator always operates in a
2-phase CCM mode, regardless of PSI_L control signal
assertion levels. During this internal, the SOFT cap is
charged by 43µA current source. If the SOFT capacitor is
selected to be 47nF, the SOFT ramp will be at 0.9mV/s
slewrate. Once VOUT is within 10% of the VID voltage,
approximately 7ms later, PGOOD is asserted HIGH. Typical
start-up timing is shown in Figure 28. The SOFT cap is
charged/discharged by approximate 200µA after the
start-up. Therefore, VOUT slews at about 4mV/s to the
voltage set by the VID pins.
VDD
VR_ON
100µs
d_----V_---
dt
≈
4_----3_----µ_----A_--
C_soft
SOFT AND Vo
~7.6ms
PGOOD
FIGURE 28. SOFT START WAVEFORMS
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs per Table 1. The entire VID
table is presented in the AMD specification.The ISL6264 will
control the no-load output voltage to an accuracy of ±0.5%
over the range of 0.75V to 1.5V.
TABLE 1. V_ID TABLE FOR AMD 6-BIT V_ID CPU
VID5 VID4 VID3 VID2 VID1 VID0
VOUT
(V)
0
0
0
0
0
0
1.5500
0
0
0
0
0
1
1.5250
0
0
0
0
1
0
1.5000
0
0
0
0
1
1
1.4750
0
0
0
1
0
0
1.4500
0
0
0
1
0
1
1.4250
0
0
0
1
1
0
1.4000
0
0
0
1
1
1
1.3750
0
0
1
0
0
0
1.3500
0
0
1
0
0
1
1.3250
0
0
1
0
1
0
1.3000
0
0
1
0
1
1
1.2750
0
0
1
1
0
0
1.2500
0
0
1
1
0
1
1.2250
0
0
1
1
1
0
1.2000
0
0
1
1
1
1
1.1750
0
1
0
0
0
0
1.1500
0
1
0
0
0
1
1.1250
0
1
0
0
1
0
1.1000
0
1
0
1
1
0
1.0000
0
1
0
1
1
1
0.9750
0
1
1
0
0
0
0.9500
0
1
1
0
0
1
0.9250
15
FN6359.1
October 16, 2006