80960JA Datasheet, PDF (9/77 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 2.
80960Jx Block Diagram
CLKIN
PLL, Clocks,
Power Mgmt
TAP _{Boundary Scan}
5
Controller
8-Set
Local Register Cache
128
Multiply
Divide
Unit
Instruction Cache
80960JA - 2K
80960JF/JD - 4K
80960JT - 16K
Two-Way Set Associative
Instruction Sequencer
Constants Control
32-bit buses
address / data
Physical Region
Configuration
Bus
Control Unit
Bus Request
Queues
Control
21
Address/
Data Bus
32
Two 32-Bit
Timers
Interrupt
Programmable ^Port
Interrupt Controller
9
Execution
and
Address
Generation
Unit
Memory
Interface
Unit
Memory-Mapped
Register Interface
Global / Local
Register File
SRC1 SRC2 DEST
effective
address
32-bit Address
32-bit Data
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
1K Data RAM
Direct Mapped
Data Cache
80960JA - 1K
80960JF/JD - 2K
80960JT - 4K
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 Core Architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core’s performance include:
• Core operates at the bus speed with the 80960JA/JF
• Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline break latency
• Register and resource scoreboarding allow overlapped instruction execution
• 128-bit register bus speeds local register caching
• Two-way set associative, integrated instruction cache
• Direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait state program data
Advance Information Datasheet
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