80960JA Datasheet, PDF (68/77 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JA/JF/JD/JT 3.3 V Microprocessor
5.1
Figure 43.
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.
The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET is
asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address.
Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV input signal indicates completion of each transfer. When data is
not ready, the processor can wait as long as necessary for the memory or I/O device to respond.
After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a
burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word.
The processor asserts the BLAST signal during the last Tw/Td states of an access. Once all data words
transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover.
The processor remains in the Tr state until RDYRCV is deasserted. When the recovery state
completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the
bus enters the Ta state to transmit the new address.
Bus States with Arbitration
(READY AND BURST)
OR NOT READY
Tw/Td
Ta
RECOVERED AND
REQUEST
PENDING AND (NO
HOLD OR LOCKED)
READY AND NO BURST
REQUEST PENDING
AND (NO HOLD OR
LOCKED)
NO REQUEST
AND (NO HOLD
OR LOCKED)
REQUEST
PENDING AND
NO HOLD
Ti
ONCE & RESET
DEASSERTION
NO REQUEST
AND NO HOLD
RECOVERED AND
NO REQUEST AND
(NO HOLD OR
LOCKED)
NOT
RECOVERED
Tr
RECOVERED AND
HOLD AND NOT
LOCKED
Th
To
RESET
Ti — IDLE STATE
Ta — ADDRESS STATE
Tw / Td — WAIT/DATA STATE
Tr — RECOVERY STATE
Th — HOLD STATE
To — ONCE STATE
HOLD AND
NOT LOCKED
HOLD
READY — RDYRCV ASSERTED
NOT READY — RDYRCV NOT ASSERTED
BURST — BLAST NOT ASSERTED
NO BURST — BLAST ASSERTED
RECOVERED — RDYRCV NOT ASSERTED
NOT RECOVERED — RDYRCV ASSERTED
REQUEST PENDING — NEW TRANSACTION
NO REQUEST — NO NEW TRANSACTION
HOLD — HOLD REQUEST ASSERTED
NO HOLD — HOLD REQUEST NOT ASSERTED
LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS
RESET — RESET ASSERTED
ONCE — ONCE ASSERTED
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