80960JA Datasheet, PDF (19/77 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3.
Pin Description — External Bus Signals (Sheet 3 of 3)
NAME
TYPE
DESCRIPTION
BLAST
RDYRCV
LOCK/
ONCE
HOLD
HOLDA
BSTAT
O
R(1)
H(Z)
P(1)
I
S(L)
I/O
S(L)
R(H)
H(Z)
P(1)
I
S(L)
O
R(Q)
H(1)
P(Q)
O
R(0)
H(Q)
P(0)
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses. BLAST remains active as long as
wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final
data transfer in a bus cycle.
0 = last data transfer
1 = not last data transfer
READY/RECOVER indicates that data on AD lines can be sampled or removed. If
RDYRCV is not asserted during a T_d cycle, the T_d cycle is extended to the next cycle
by inserting a wait state (T_w).
0 = sample data
1 = don’t sample data
The RDYRCV pin has another function during the recovery (T_r) state. The processor
continues to insert additional recovery states until it samples the pin HIGH. This
function gives slow external devices more time to float their buffers before the
processor begins to drive address again.
0 = insert wait states
1 = recovery complete
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
LOCK output is asserted in the first clock of an atomic operation and deasserted in
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK. This prevents external agents from accessing memory involved
in semaphore operations.
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
ONCE MODE: The processor samples the ONCE input during reset. If it is asserted
LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the
processor stops all clocks and floats all output pins. The pin has a weak internal
pullup which is active during reset to ensure normal operation when the pin is left
unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the T_h state. When
HOLD is deasserted, the processor deasserts HOLDA and enters either the T_i or T_a
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. The processor can grant HOLD requests and enter
the T_h state during reset and while halted as well as during regular operation.
0 = hold not acknowledged
1 = hold acknowledged
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see i960^® Jx Microprocessor Developer’s Manual (272483).
Arbitration logic can examine this signal to determine when an external bus master
should acquire/relinquish the bus.
0 = no potential stall
1 = potential stall
Advance Information Datasheet
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