80960JA Datasheet, PDF (69/77 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JA/JF/JD/JT 3.3 V Microprocessor
5.2
Table 25.
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins.
Table 25 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that
contain “CTL” select the direction of bidirectional pins or HIGHZ output pins. If a “1” is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.
Boundary-Scan Register Bit Order
Bit
Signal
Input/
Output
Bit
Signal
Input/
Output
Bit
Signal
Input/
Output
0 RDYRCV (TDI)
I
24
DEN
O
48
AD17
I/O
1
HOLD
I
25
HOLDA
O
49
AD16
I/O
2
XINT0
I
26
ALE
O
50
AD15
I/O
3
XINT1
I
27
LOCK/ONCE
cell
Enable cell¹
51
AD14
I/O
4
XINT2
I
28 LOCK/ONCE
I/O
52
AD13
I/O
5
XINT3
I
29
BSTAT
O
53
AD12
I/O
6
XINT4
I
30
BE0
O
54
AD cells
Enable
cell¹
7
XINT5
I
31
BE1
O
55
AD11
I/O
8
XINT6
I
32
BE2
O
56
AD10
I/O
9
XINT7
I
33
BE3
O
57
AD9
I/O
10
NMI
I
34
AD31
I/O
58
AD8
I/O
11
FAIL
I
35
AD30
I/O
59
AD7
I/O
12
ALE
O
36
AD29
I/O
60
AD6
I/O
13 WIDTH/HLTD1
O
37
AD28
I/O
61
AD5
I/O
14 WIDTH/HLTD0
O
38
AD27
I/O
62
AD4
I/O
15
A2
O
39
AD26
I/O
63
AD3
I/O
16
A3
O
40
17
CONTROL1 Enable cell¹ 41
18
CONTROL2 Enable cell¹ 42
AD25
AD24
AD23
I/O
64
AD2
I/O
I/O
65
AD1
I/O
I/O
66
AD0
I/O
19
BLAST
O
43
AD22
I/O
67 CLKIN
I
20
D/C
O
44
AD21
I/O
68 RESET
I
21
ADS
O
45
AD20
I/O
69
STEST
(TDO)
I
22
W/R
O
46
AD19
I/O
23
DT/R
O
47
AD18
I/O
NOTE:
1. Enable cells are active low.
Advance Information Datasheet
69