80960JA Datasheet, PDF (58/77 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JA/JF/JD/JT 3.3 V Microprocessor
5.0
Bus Functional Waveforms
Figure 33.
Figure 33 through Figure 38 illustrate typical 80960Jx bus transactions. Figure 39 depicts the bus
arbitration sequence. Figure 40 illustrates the processor reset sequence from the time power is
applied to the device. Figure 41 illustrates the processor reset sequence when the processor is in
operation. Figure 42 illustrates the processor ONCE sequence from the time power is applied to the
device. Figure 44 and Figure 45 also show accesses on 32-bit buses. Table 27 through Table 29
summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to
data alignment.
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
T_a T_d T_r
T_i
T_i T_a T_d
T_r
T_i T_i
CLKIN
AD31:0
ADDR
D
In
Invalid ADDR
DATA Out
ALE
ADS
A3:2
BE3:0
WIDTH1:0
10
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF030A
58
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